Method of manufacturing semiconductor device having high voltage ESD protective diode
View Patent ↗A high voltage ESD protective diode having high avalanche withstand capability and capable of being formed by using manufacturing steps identical with those for a high voltage transistor to be protected, the device having a structure in which a gate oxide film is formed over a substrate surface at a PN junction formed of an N type low concentration semiconductor substrate constituting a cathode region and a P type low concentration diffusion region constituting an anode region, and a gate electrode which is disposed overriding the gate oxide film and a field oxide film is connected electrically by way of a gate plug with an anode electrode, whereby an electric field at the PN junction is moderated upon avalanche breakdown to obtain a high avalanche withstand capability. Further, the withstand voltage can be adjusted by changing the length of the field oxide film.
1. A method of manufacturing a semiconductor device configured by forming a diode having a first electrode and a second electrode different from the first electrode as terminals over a semiconductor substrate, the method comprising:
(a) providing the semiconductor substrate of a first conduction type;
(b) forming a low concentration diffusion region of a second conduction type which is a conduction type opposite to the first conduction type over the semiconductor substrate;
(c) forming a gate oxide film over a surface of the low concentration diffusion region overriding a PN junction formed by contact between the first conduction type and the second conduction type;
(d) forming a gate electrode above the gate oxide film;
(e) forming a first high concentration diffusion region of the first conduction type having an impurity concentration higher than that of the semiconductor substrate;
(f) forming a second high concentration diffusion region of the second conduction type having an impurity concentration higher than that of the low concentration diffusion region;
(g) forming a first electrode so as to be connected electrically with the first high concentration diffusion region; and
(h) forming a second electrode so as to be connected electrically with the gate electrode and the second high concentration diffusion region.
2. The method of manufacturing a semiconductor device according to claim 1 , further comprising:
(i) forming a field oxide film over the surface of the semiconductor substrate,
wherein the step (d) is a step of forming the gate electrode above the gate oxide film and the field oxide film overriding both of the films.
3. The method of manufacturing a semiconductor device according to claim 2 ,
wherein the length from the PN junction to the field oxide film of the diode is 1.7 μm or more.
4. The method of manufacturing a semiconductor device according to claim 2 ,
wherein a multi-channel structure is formed by including two or more regions having electrodes each paired with a drift region to one of a region having the first electrode and a region having the second electrode.
5. The method of manufacturing a semiconductor device according to claim 2 ,
wherein the semiconductor substrate is an SOI substrate in which an insulation layer is formed inside a silicon layer.
6. The method of manufacturing a semiconductor device according to claim 2 , configured by integrally forming a LDMOS transistor together with the diode over a common semiconductor substrate, the LDMOS transistor including:
a well region of the second conduction type formed over a surface layer of a semiconductor region of the first conduction type;
a drain region of the first conduction type formed over a surface layer of a semiconductor region selectively spaced from the well region;
a source region of the second conduction type formed to the surface layer of the well region;
a gate electrode disposed by way of a gate oxide film to the well region;
a source electrode in contact with a well feed region over the well region and the source region of the second conduction type is further formed integrally with the diode over a common semiconductor substrate, and
a field oxide film formed over the semiconductor substrate,
wherein the step (b) is a step of forming the low concentration diffusion region simultaneously with the well region of the LDMOS transistor over the semiconductor substrate,
wherein the step (e) is a step of forming the first high concentration diffusion region simultaneously with the drain region of the LDMOS transistor,
wherein the step (f) is a step of forming the second high concentration diffusion region simultaneously with the well feed region of the LDMOS transistor,
wherein the step (c) is a step of forming the gate oxide film of the diode simultaneously with the gate oxide film of the LDMOS transistor,
wherein the step (d), is a step of forming the gate electrode of the diode simultaneously with the gate electrode of the LDMOS transistor, and
wherein the step (i) is a step of forming the field oxide film of the diode simultaneously with the field oxide film of the LDMOS transistor.
7. The method of manufacturing a semiconductor device according to claim 6 ,
wherein the length of the field oxide film of the diode is shorter than that of the field oxide film of the LDMOS transistor.
8. The method of manufacturing a semiconductor device according to claim 6 ,
wherein the length from the PN junction to the field oxide film of the diode is 1.7 μm or more.
9. The method of manufacturing a semiconductor device according to claim 6 ,
wherein a multi-channel structure is formed by including two or more regions having electrodes each paired with a drift region to one of a region having the first electrode and a region having the second electrode.
10. The method of manufacturing a semiconductor device according to claim 6 ,
wherein the semiconductor substrate is an SOI substrate in which an insulation layer is formed inside a silicon layer.