METHOD AND SYSTEM FOR DETERMINING A CACHE MEMORY CONFIGURATION FOR TESTING
A method and computer device for determining the cache memory configuration. The method includes allocating an amount of cache memory from a first memory level of the cache memory, and determining a read transfer time for the allocated amount of cache memory. The allocated amount of cache memory then is increased and the read transfer time for the increased allocated amount of cache memory is determined. The allocated amount of cache memory continues to be increased and the read transfer time determined for the each allocated amount until all of the cache memory in all of the cache memory levels has been allocated. The cache memory configuration is determined based on the read transfer times from the allocated portions of the cache memory. The determined cache memory configuration includes the number of cache memory levels and the respective capacities of each cache memory level.
1 . A method for determining a cache memory configuration within a computer system, wherein the cache memory includes a plurality of cache memory levels, the method comprising:
allocating a first amount of cache memory from a first memory level of the plurality of cache memory levels;
determining a read transfer time for the allocated amount of cache memory;
increasing the allocation amount of the cache memory;
repeating the read transfer time determining step and the cache memory allocation increasing step until all of the cache memory in all of the cache memory levels has been allocated; and
determining the cache memory configuration based on the determined read transfer times of the plurality of the cache memory levels.
2 . The method as recited in claim 1 , wherein the computer system includes a CPU, and wherein determining a read transfer time for the allocated amount of cache memory includes the CPU writing data in the allocated cache memory and then reading the data from the allocated cache memory.
3 . The method as recited in claim 2 , wherein the computer system includes a plurality of CPUs, and wherein determining a read transfer time for the allocated amount of cache memory includes each of the plurality of CPUs writing data in the allocated cache memory and then reading the data from the allocated cache memory.
4 . The method as recited in claim 2 , wherein the CPU reads the data from the allocated cache memory multiple times.
5 . The method as recited in claim 2 , wherein the CPU reads the data from the allocated cache memory on a cacheline basis.
6 . The method as recited in claim 1 , wherein determining the cache memory configuration based on the determined read transfer times of the plurality of the cache memory levels includes building a table configured to record access times and the capacity of each of the plurality of cache memory levels.
7 . The method as recited in claim 1 , wherein the computer system includes a plurality of CPUs, and wherein the cache memory allocating step, the read transfer time determining step, the cache memory allocation increasing step and the repeating step are performed by each of the plurality of CPUs.
8 . The method as recited in claim 1 , wherein, when the allocated amount of cache memory exceeds the capacity of the current cache memory level, at least a portion of the next cache memory level becomes part of the allocated amount of cache memory.
9 . The method as recited in claim 1 , wherein the capacity of a cache memory level is determined based on a change in read transfer time.
10 . A computing device, comprising:
a processor;
a memory element coupled to the processor, wherein the memory element includes cache memory having a plurality of cache memory levels; and
a cache memory configuration interrogation module coupled to the processor and to the memory element, wherein the cache memory configuration interrogation module is configured to
allocate a first amount of cache memory from a first cache memory level of the plurality of cache memory levels;
determine a read transfer time for the allocated amount of cache memory;
increase the allocation amount of the cache memory;
repeat the read transfer time determination and the cache memory allocation increase until all of the cache memory in all of the plurality of cache memory levels has been allocated; and
determine the cache memory configuration based on the determined read transfer times of the plurality of the cache memory levels.
11 . The computer device as recited in claim 10 , wherein each cache memory level includes a plurality of cachelines of data storage units, and wherein the cache memory configuration interrogation module is configured to determine a read transfer time for the allocated amount of cache memory by writing at least one data byte in each cacheline of the allocated amount of cache memory and then reading the at least one data byte in each cacheline of the allocated amount of cache memory.
12 . The computer device as recited in claim 11 , wherein the cache memory configuration interrogation module is configured to set a start write time, write at least one data byte in each cacheline of the allocated amount of cache memory multiple times, set an end write time, and calculate a write time per byte based on the start write time and the end write time.
13 . The computer device as recited in claim 11 , wherein the cache memory configuration interrogation module is configured to set a start read time, read at least one data byte in each cacheline of the allocated amount of cache memory multiple times, set an end read time, and calculate a read time per byte based on the start read time and the end read time.
14 . The computer device as recited in claim 10 , wherein the cache memory configuration interrogation module is configured to write data to the allocated amount of cache memory and read data from the allocated amount of cache memory on a cacheline basis.
15 . The computer device as recited in claim 10 , wherein the cache memory configuration interrogation module is configured to establish a data structure configured to store data write timings and data read timings for each level of cache memory, and wherein the cache memory configuration interrogation module is configured to determine the cache memory configuration based on the information stored in the data structure.
16 . The computer device as recited in claim 10 , wherein, when the allocated amount of cache memory exceeds the capacity of the current cache memory level, the cache memory configuration interrogation module allocates at least a portion of the next cache memory level to become part of the allocated amount of cache memory.
17 . The computer device as recited in claim 10 , wherein the capacity of a cache memory level is determined based on a change in read transfer time.
18 . A non-transitory computer readable medium having instructions stored thereon which, when executed by a processor, carry out a method for determining a cache memory configuration, the instructions comprising:
instructions for allocating a first amount of cache memory from a first memory level of a plurality of cache memory levels of the cache memory;
instructions for determining a read transfer time for the allocated amount of cache memory;
instructions for increasing the allocation amount of the cache memory;
instructions for repeating the read transfer time determining step and the cache memory allocation increasing step until all of the cache memory in all of the cache memory levels has been allocated; and
instructions for determining the cache memory configuration based on the determined read transfer times of the plurality of the cache memory levels.
19 . The non-transitory computer readable medium as recited in claim 18 , wherein the instructions for determining a read transfer time for the allocated amount of cache memory includes instructions for writing at least one data byte in each of a plurality of portions of the allocated amount of cache memory and then reading the at least one data byte in each of the plurality of portions of the allocated amount of cache memory.