Photodetector isolation in image sensors
View Patent ↗Shallow trench isolation regions are disposed in an n-type silicon semiconductor layer laterally adjacent to a collection region of a photodetector and laterally adjacent to a charge-to-voltage conversion region. The shallow trench isolation regions each include a trench disposed in the silicon semiconductor layer and a first dielectric structure disposed along an interior bottom and sidewalls of each trench. A second dielectric structure is disposed over the pinning layer. The dielectric structures include a silicon nitride layer disposed over an oxide layer. An n-type isolation layer is disposed along only a portion of the exterior bottom of the trench and the exterior sidewall of the trench immediately adjacent to the photodetector. The n-type isolation layer is not disposed along the remaining portion of the bottom or the opposing exterior sidewall of the trench.
1. A method for producing a shallow trench isolation region in a silicon semiconductor layer having an n conductivity type immediately adjacent to a photodetector, wherein the photodetector includes a storage region having a p conductivity type disposed in the silicon semiconductor layer, the method comprising:
forming a trench in the silicon semiconductor layer;
forming a liner oxide layer along an interior bottom and interior sidewalls of the trench;
forming a silicon nitride layer over the liner oxide layer;
filling the trench with a dielectric material; and
implanting a dopant having the n conductivity type into the silicon semiconductor layer only partially along a bottom of the trench and only along a sidewall of the trench immediately adjacent to where the storage region of the photodetector will be subsequently formed.
2. The method as in claim 1 , further comprising forming a pinning layer having the n conductivity type over the storage region.
3. The method as in claim 2 , further comprising:
forming a gate oxide layer over the pinning layer and the silicon semiconductor layer; and
forming a silicon nitride layer over at least a portion of the gate oxide layer.