IP Library Granted Patent US 8,937,349
Granted Patent B2
US 8,937,349 · App. 12/967,857 · Granted Jan 20, 2015

Semiconductor component and manufacturing method thereof

Inventor: Koichi Amari (Kanagawa, JP)
Assignee: Sony Corporation
H01L29/66545H01L29/4236H01L29/66583H01L29/66621H01L29/7834H01L29/7843
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Quick Facts
Patent No.
US 8,937,349
App. No.
12/967,857
Granted
Jan 20, 2015
Kind
B2
Abstract

A semiconductor component includes: a semiconductor substrate; and a semiconductor device provided thereon, the device being a field-effect transistor that includes: a gate insulating film provided on the substrate; a gate electrode provided via the film; and a pair of source-drain regions provided to sandwich the electrode, the substrate including a patterned surface in a portion where the electrode is provided, the patterned surface of the substrate including a raised portion where the film is formed to cover a surface that lies on the same plane as a surface of the pair of source-drain regions, and the electrode is formed on a top surface of the film, and the patterned surface of the substrate including a recessed portion where the film is formed to cover surfaces of a groove formed toward the interior than the surface of the pair of source-drain regions, and the electrode is formed so as to fill the groove provided with the film.

Claims (30)

1. A semiconductor component comprising:

a semiconductor substrate; and

a semiconductor device on the semiconductor substrate,

wherein, in cross section,

the semiconductor device has a pair of source and drain regions in the semiconductor substrate,

at least a portion of the semiconductor substrate has a raised structure with a groove therein, where the groove extends into the semiconductor substrate and to the same depth as the deepest extent of the source-drain region,

a gate insulating film lines all interior surfaces of the groove,

a gate electrode is within the groove of the raised structure and surrounded on at least three sides by the gate insulating film, and

the pair of source region-drain regions are at opposite sides of the gate electrode.

2. The semiconductor component according to claim 1 , wherein the groove has a side surface along a depth direction of the semiconductor substrate.

3. The semiconductor component according to claim 1 , wherein the groove on the patterned surface of the semiconductor substrate has a surface slanted with respect to a depth direction of the semiconductor substrate.

4. The semiconductor component according to claim 3 , wherein the slanted surface of the groove on the patterned surface of the semiconductor substrate lies on a (111) plane.

5. The semiconductor component according to claim 1 , wherein the pair of source-drain regions has the same shape for the raised structure of the semiconductor substrate.

6. The semiconductor component according to claim 5 , wherein the pair of source-drain regions has a flat top surface, and the same depth in the semiconductor substrate as the raised structure.

7. A method for manufacturing a semiconductor component, the method comprising the steps of:

providing a semiconductor substrate with a pair of source region-drain regions therein and at least a portion of the semiconductor substrate having a raised structure with a groove therein, where the groove extends into the semiconductor substrate and to the same depth as the deepest extent of the source-drain region;

lining all interior surfaces of the groove with a gate insulating film;

providing a gate electrode within the groove of the raised structure such that the gate electrode is surrounded on at least three sides by the gate insulating film, and

providing the pair of source region-drain regions at opposite sides of the gate electrode.

8. The method according to claim 7 , further comprising the steps of:

forming a dummy gate insulating film on at least a portion of a surface of the semiconductor substrate;

forming a dummy gate electrode on the dummy gate insulating film;

forming the pair of source-drain regions so that the dummy gate electrode is in-between a source region and a drain region;

forming a planarizing film on the surface of the semiconductor substrate so as to expose an upper surface of the dummy gate electrode, and to cover an upper surface of the pair of source-drain regions;

removing the dummy gate electrode and the dummy gate insulating film so as to expose a portion of the semiconductor substrate

forming an opening in the exposed surface portion;

etching the opening of the semiconductor substrate to provide the raised structure with the groove therein;

depositing an insulating film over the all interior surfaces of the groove; and

depositing a conductive film over the gate insulating film in the groove so as to form the gate electrode.

9. The method according to claim 7 , wherein the pair of source-drain regions is formed in the same shape as the raised structure of the semiconductor substrate.

Assignments (2)
CHANGE OF NAME Recorded Aug 25, 2021
From: SONY CORPORATION
To: SONY GROUP CORPORATION
Reel/Frame 057310/0042 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2010
From: AMARI, KOICHI
To: SONY CORPORATION
Reel/Frame 025499/0750 →
Priority Claims (1)
JP 2009-298319 · Dec 28, 2009 · national
Continuity (1)
Related Publication 20110156136A1 · Jun 30, 2011