Method for controlling voltages supplied to a processor

1. A DC/DC converter comprising:

an inductor;

a smoothing capacitor coupled to said inductor;

a controller for controlling an output voltage according to each power state of a processor operating in a transition state where a power state of said processor transitions between an active state and a predetermined sleeping state at a predetermined transition frequency; and

an arithmetic circuit for determining a transition stop condition based on power consumption of said processor and charging loss generated at said smoothing capacitor during transition of said active state, and for outputting a transition stop signal to stop said processor from transitioning to said predetermined sleeping state if said transition stop condition is satisfied;

wherein said transition stop condition is satisfied when a difference between power consumption of said processor maintaining a C0 state and power consumption of said processor operating in a transition state is smaller than said charging loss.

2. The DC/DC converter of claim 1 , wherein said arithmetic circuit determines said charging loss based on an output voltage corresponding to said active state, an output voltage corresponding to said predetermined sleeping state and a capacitance of said smoothing capacitor.

3. The DC/DC converter of claim 1 , wherein said arithmetic circuit compares a total power consumption of said processor and electric power loss of said power supply unit when said processor operates in said transition state with a total of power consumption of said processor and electric power loss of said power supply unit when said processor operates while maintaining said active state to determine said transition stop condition.

4. The DC/DC converter of claim 1 , wherein said arithmetic circuit determines said transition stop condition based on actually measured power consumption of said processor, and an output voltage and said transition frequency obtained from said processor.

5. The DC/DC converter of claim 1 , wherein said DC/DC converter further includes a timer circuit for stopping output of said transition stop signal and for making said processor operating while maintaining said active state operate in said transition state every predetermined time duration in order to allow said arithmetic circuit to determine said transition stop condition.

6. The DC/DC converter of claim 1 , wherein said arithmetic circuit obtains said capacitance of said smoothing capacitor from a resistor element having a resistance value corresponding to said capacitance of said smoothing capacitor.

7. The of claim 1 , wherein said predetermined sleeping state is a C6 state according to the Advanced Configuration and Power Interface (ACPI), during which a cache memory of said processor is powered off and an operating state of said processor is saved in a static memory.

8. A computer comprising:

a processor capable of operating in a transition state where a power state of said processor transitions between an active state and a predetermined sleeping state at a predetermined transition frequency;

a power supply unit;

a DC/DC converter, coupled to said power supply, having

an inductor;

a smoothing capacitor coupled to said inductor;

a controller for controlling an output voltage according to each power state of said processor; and an arithmetic circuit for determining a transition stop condition based on power consumption of said processor and charging loss generated at said smoothing capacitor during transition of said active state, and for outputting a transition stop signal to stop said processor from transitioning to said predetermined sleeping state if said transition stop condition is satisfied; and

a transition stop circuit, in response to said transition stop signal, for stopping an operation of said processor in said transition state;

wherein said transition stop condition is satisfied when a difference between power consumption of said processor maintaining a C0 state and power consumption of said processor operating in a transition state is smaller than said charging loss.

9. The computer of claim 8 , wherein said arithmetic circuit obtains said capacitance of said smoothing capacitor from a resistor element having a resistance value corresponding to said capacitance of said smoothing capacitor.

10. A computer comprising:

a processor capable of operating in a transition state during which a power state of said processor transitions between an active state and a predetermined sleeping state at a predetermined transition frequency;

a power supply unit and a DC/DC converter having an inductor;

a smoothing capacitor coupled to said inductor; and

a controller for controlling an output voltage in accordance with each power state of said processor operating in said transition state;

an arithmetic circuit for determining a transition stop condition based on power consumption of said processor and charging loss generated at said smoothing capacitor operating in said transition state and outputs a transition stop signal to stop transition to said predetermined sleeping state if said transition stop condition is satisfied; and

a device that changes, in response to said transition stop signal, setting of said processor so that said processor operates in a transition state where said processor transitions between said active state and a sleeping state shallower than said predetermined power state by one step;

wherein said transition stop condition is satisfied when a difference between power consumption of said processor maintaining a C0 state and power consumption of said processor operating in a transition state is smaller than said charging loss.

11. The computer of claim 10 , wherein said arithmetic circuit obtains said capacitance of said smoothing capacitor from a resistor element having a resistance value corresponding to said capacitance of said smoothing capacitor.