INTEGRATED CIRCUITS AND FABRICATION PROCESS THEREOF
An integrated circuit includes a conductive pad and a substrate. The conductive pad is used to transfer a first signal. The substrate blocks a second signal from a first region of the substrate to the conductive pad. A second region of the substrate insulates a third region of the substrate from the first region. The first and third regions include a first type of semiconductor and the second region includes a second type of semiconductor. In addition, a first shadow obtained by perpendicularly projecting the third region onto a surface of the substrate overlaps with a second shadow obtained by perpendicularly projecting the conductive pad onto the surface.
1 . An integrated circuit comprising:
a conductive pad for transferring a first signal; and
a substrate capable of blocking a second signal from a first region of said substrate to said conductive pad, wherein a second region of said substrate insulates a third region of said substrate from said first region, wherein said first and third regions comprise a first type of semiconductor and said second region comprises a second type of semiconductor, and wherein a first shadow obtained by perpendicularly projecting said third region onto a surface of said substrate overlaps with a second shadow obtained by perpendicularly projecting said conductive pad onto said surface.
2 . The integrated circuit as claimed in claim 1 , wherein said conductive pad comprises a metal pad.
3 . The integrated circuit as claimed in claim 1 , further comprising:
an amplifier operable for receiving said first signal via said conductive pad.
4 . The integrated circuit as claimed in claim 1 , further comprising:
an oscillator operable for providing said first signal via said conductive pad.
5 . The integrated circuit as claimed in claim 1 , wherein said first signal has a frequency that is greater than 900 MHz.
6 . The integrated circuit as claimed in claim 1 , wherein said second signal comprises an interfering signal caused by digital circuitry of said integrated circuit.
7 . The integrated circuit as claimed in claim 1 , wherein said second signal comprises an interfering signal caused by radio-frequency circuitry of said integrated circuit.
8 . The integrated circuit as claimed in claim 1 , wherein said first type of semiconductor comprises p-type semiconductor and said second type of semiconductor comprises n-type semiconductor.
9 . The integrated circuit as claimed in claim 8 , wherein said second region has a substantially constant voltage level that is higher than a voltage level at said first region and higher than a voltage level at said third region.
10 . The integrated circuit as claimed in claim 1 , wherein said first, second and third regions form a transistor.
11 . A method for transferring a first signal, said method comprising:
transferring said first signal via a conductive pad;
blocking a second signal from a first region of a substrate to said conductive pad; and
insulating a second region of said substrate from said first region by a third region of said substrate;
wherein said first and second regions comprise a first type of semiconductor and said third region comprises a second type of semiconductor, and wherein a first shadow obtained by perpendicularly projecting said second region onto a surface of said substrate overlaps with a second shadow obtained by perpendicularly projecting said conductive pad onto said surface.
12 . The method as claimed in claim 11 , wherein said first signal has a frequency that is greater than 900 MHz.
13 . The method as claimed in claim 11 , wherein said first type of semiconductor comprises p-type semiconductor and said second type of semiconductor comprises n-type semiconductor.
14 . The method as claimed in claim 13 , further comprising:
controlling a voltage level at said third region to be substantially constant and higher than a voltage level at said first region and higher than a voltage level at said second region.
15 . A method for fabricating an integrated circuit, said method comprising:
forming a buried-layer atop a first region of a substrate;
forming a well atop an epitaxial (epi) layer grown atop said first region so that a second region that includes said buried-layer and said well insulates a third region from said first region; and
depositing a conductive pad atop an epi region grown atop said epi layer,
wherein said first and third regions comprise a first type of semiconductor and said second region comprises a second type of semiconductor, and wherein a first shadow obtained by perpendicularly projecting said third region onto a surface of said substrate overlaps with a second shadow obtained by perpendicularly projecting said conductive pad onto said surface.
16 . The method as claimed in claim 15 , further comprising:
forming a conductive channel in said epi region to connect said second region to a voltage input terminal.
17 . The method as claimed in claim 15 , wherein said third region is part of said epi layer.
18 . The method as claimed in claim 15 , wherein said epi region comprises oxide to insulate said conductive pad from said substrate.
19 . The method as claimed in claim 15 , wherein said first type of semiconductor comprises p-type semiconductor and said second type of semiconductor comprises n-type semiconductor.