Power semiconductor device with new guard ring termination design and method for producing same
View Patent ↗A power semiconductor device, such as a power diode, and a method for producing such a device, are disclosed. The device includes a first layer of a first conductivity type, a second layer of a second conductivity type arranged in a central region on a first main side of the first layer, a third electrically conductive layer arranged on the second layer, and a fourth electrically conductive layer arranged on the first layer at a second main side opposite to the first main side. A junction termination region surrounds the second layer with self-contained sub-regions of the second conductivity type. A spacer region is arranged between the second layer and the junction termination region and includes a self-contained spacer sub-region of the second conductivity type which is electrically disconnected from the second layer. This spacer sub-region has a width for enabling a reliable alignment of a shadow mask during an ion implantation such that an implanted lifetime control region having carrier lifetime reducing defects may be restricted to a central area while no such defects are implanted into the junction termination region to improve electrical characteristics.
1. Power semiconductor device with an active region comprising:
a first layer of a first conductivity type, which has a first main side and a second main side opposite the first main side;
a second layer of a second conductivity type, which is arranged in a central region on the first main side, wherein the second layer corresponds to an active region;
a junction termination region arranged in a circumferential region on the first main side and surrounding the second layer, the junction termination region comprising at least one sub-region of the second conductivity type implemented into a sub-region of the first conductivity type, wherein subsequent spacer sub-regions laterally enclose each other;
a third electrically conductive layer, which is arranged on the second layer on a side opposite the first layer;
a fourth electrically conductive layer, which is arranged on the second main side;
a spacer region arranged in an intermediate region on the first main side between the second layer and the junction termination region and surrounding the second layer, the spacer region comprising a spacer sub-region of the second conductivity type implemented into a sub-region of the first conductivity type, wherein the spacer sub-region of the second conductivity type laterally encloses the sub-region of the first conductivity type, such that the spacer sub-region is electrically disconnected from the second layer; and
a lifetime control region comprising defects reducing a carrier lifetime within adjacent semiconductor material, the lifetime control region extending at least throughout the second layer and throughout a portion of the spacer sub-region and not extending into the junction termination region.
2. The power semiconductor device of claim 1 , wherein a width of the spacer sub-region of the second conductivity type is larger than a width of the at least one sub-region of the second conductivity type.
3. The power semiconductor device of claim 2 , wherein ions forming the lifetime control region comprise hydrogen ions or helium ions.
4. The power semiconductor device of claim 3 , comprising:
a layer covering the junction termination region and at least a portion of the spacer region.
5. The power semiconductor device of claim 3 , wherein the power semiconductor device is a power diode.
6. The power semiconductor device of claim 1 , wherein a width of the spacer sub-region of the second conductivity type is two times larger than a width of the at least one sub-region of the second conductivity type.
7. The power semiconductor device of claim 1 , wherein a width of the spacer sub-region of the second conductivity type is five times larger than a width of the at least one sub-region of the second conductivity type.
8. The power semiconductor device of claim 1 , wherein the spacer sub-region has a width of at least 10 μm.
9. The power semiconductor device of claim 1 , wherein ions forming the lifetime control region comprise hydrogen ions or helium ions.
10. The power semiconductor device of claim 1 , comprising:
a layer covering the junction termination region and at least a portion of the spacer region.
11. The power semiconductor device of claim 10 , wherein the layer comprises:
a polymer material.
12. The power semiconductor device of claim 1 , wherein the power semiconductor device is a power diode.