Regulating power consumption of digital circuitry using a multi-layer ring oscillator
View Patent ↗A computing device is disclosed comprising digital circuitry fabricated on a multi-layer integrated circuit including a first layer and a second layer, and a multi-layer ring oscillator operable to generate a propagation delay frequency representing a propagation delay of the integrated circuit, wherein the multi-layer ring oscillator comprises a first interconnect fabricated on the first layer and a second interconnect fabricated on the second layer. The propagation delay frequency is compared to a reference frequency to generate a frequency error, and at least one of a supply voltage and a clocking frequency applied to the digital circuitry is adjusted in response to the frequency error.
1. A computing device comprising:
digital circuitry fabricated on a first layer and a second layer of a multi-layer integrated circuit;
a first multi-layer ring oscillator operable to generate a propagation delay frequency representing a propagation delay of the integrated circuit, wherein the first multi-layer ring oscillator comprises a first interconnect fabricated on the first layer and a second interconnect fabricated on the second layer;
a reference frequency;
a frequency comparator for generating a frequency error representing a difference between the reference frequency and the propagation delay frequency; and
an adjustable circuit, responsive to the frequency error, for adjusting at least one of a supply voltage and a clocking frequency applied to the digital circuitry.
2. The computing device as recited in claim 1 , wherein the first interconnect comprises a first feedback path and the second interconnect comprises a second feedback path.
3. The computing device as recited in claim 1 , wherein:
the first interconnect connects an output of a first inverting element to an input of a second inverting element; and
the second interconnect connects an output of the second inverting element to an input of a third inverting element.
4. The computing device as recited in claim 2 , wherein the first multi-layer ring oscillator further comprises:
a first AND gate having a first active high input coupled to the first feedback path and a second active high input coupled to the second feedback path; and
a second AND gate having a first active low input coupled to the first feedback path and a second active low input coupled to the second feedback path.
5. The computing device as recited in claim 4 , wherein:
the first multi-layer ring oscillator further comprises a third feedback path shorter than the first and second feedback paths; and
the third feedback path enables an output of the first and second AND gates.
6. The computing device as recited in claim 1 , wherein the first multi-layer ring oscillator comprises a configurable number of inverting elements.
7. The computing device as recited in claim 6 , wherein the first multi-layer ring oscillator further comprises a multiplexer for configuring the number of inverting elements.
8. The computing device as recited in claim 1 , wherein at least one of the first and second interconnects comprises a serpentine pattern.
9. The computing device as recited in claim 8 , further comprising a second multi-layer ring oscillator comprising a third interconnect fabricated on a third layer and a fourth interconnect fabricated on a fourth layer, wherein the first, second, third and fourth layers are interleaved.
10. The computing device as recited in claim 9 , wherein:
at least one of the third and fourth interconnects comprises a serpentine pattern;
the first interconnect comprises a serpentine pattern oriented in a first direction; and
the third interconnect comprises a serpentine pattern oriented in a second direction different from the first direction.
11. The computing device as recited in claim 10 , wherein the first and second directions are orthogonal.
12. The computing device as recited in claim 1 , further comprising a logic circuit operable to selectively omit one of the first and second interconnects from the first multi-layer ring oscillator.
13. A method of operating a computing device comprising digital circuitry fabricated on a first layer and a second layer of a multi-layer integrated circuit, a first multi-layer ring oscillator operable to generate a propagation delay frequency representing a propagation delay of the integrated circuit, wherein the first multi-layer ring oscillator comprises a first interconnect fabricated on the first layer and a second interconnect fabricated on the second layer, the method comprising:
generating a frequency error representing a difference between a reference frequency and the propagation delay frequency; and
adjusting at least one of a supply voltage and a clocking frequency applied to the digital circuitry in response to the frequency error.
14. The method as recited in claim 13 , wherein the first interconnect comprises a first feedback path and the second interconnect comprises a second feedback path.
15. The method as recited in claim 13 , wherein:
the first interconnect connects an output of a first inverting element to an input of a second inverting element; and
the second interconnect connects an output of the second inverting element to an input of a third inverting element.
16. The method as recited in claim 14 , wherein the first multi-layer ring oscillator further comprises:
a first AND gate having a first active high input coupled to the first feedback path and a second active high input coupled to the second feedback path; and
a second AND gate having a first active low input coupled to the first feedback path and a second active low input coupled to the second feedback path.
17. The method as recited in claim 16 , wherein:
the first multi-layer ring oscillator further comprises a third feedback path shorter than the first and second feedback paths; and
the third feedback path enables an output of the first and second AND gates.
18. The method as recited in claim 13 , wherein the first multi-layer ring oscillator comprises a configurable number of inverting elements, the method further comprising configuring the number of inverting elements in the first multi-layer ring oscillator.
19. The method as recited in claim 18 , wherein the first multi-layer ring oscillator further comprises a multiplexer for configuring the number of inverting elements.
20. The method as recited in claim 13 , wherein at least one of the first and second interconnects comprises a serpentine pattern.
21. The method as recited in claim 20 , further comprising a second multi-layer ring oscillator comprising a third interconnect fabricated on a third layer and a fourth interconnect fabricated on a fourth layer, wherein the first, second, third and fourth layers are interleaved.
22. The method as recited in claim 21 , wherein:
at least one of the third and fourth interconnects comprises a serpentine pattern;
the first interconnect comprises a serpentine pattern oriented in a first direction; and
the third interconnect comprises a serpentine pattern oriented in a second direction different from the first direction.
23. The method as recited in claim 22 , wherein the first and second directions are orthogonal.
24. The method as recited in claim 13 , further comprising selectively omitting one of the first and second interconnects from the first multi-layer ring oscillator.