IP Library Granted Patent US 8,866,718
Granted Patent B2
US 8,866,718 · App. 12/972,743 · Granted Oct 21, 2014

Drive circuit and display device

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Quick Facts
Patent No.
US 8,866,718
App. No.
12/972,743
Granted
Oct 21, 2014
Kind
B2
Abstract

The present invention provides a drive circuit and a display device realizing reduced variations in both a trailing timing and a rising timing of output voltage. The drive circuit includes an input-side inverter circuit and an output-side inverter circuit connected to each other in series and inserted between a high-voltage line and a low-voltage line. The output-side inverter circuit includes: a first transistor having a drain connected to the high-voltage line side and a source connected to an output side of the output-side inverter circuit; a second transistor having a drain connected to the low-voltage line side and a source connected to an output side of the output-side inverter circuit; and a correction circuit correcting gate voltage of the first and second transistors.

Claims (30)

1. A drive circuit comprising an input-side inverter circuit and an output-side inverter circuit connected to each other in series and inserted between a high-voltage line and a low-voltage line,

wherein the output-side inverter circuit includes:

a first transistor having a drain connected to a high-voltage line side and a source connected to an output side of the output-side inverter circuit;

a second transistor having a drain connected to a low-voltage line side and a source connected to an output side of the output-side inverter circuit;

a third transistor of which a first of a source or drain is connected to a gate side of the first transistor and of which a second of the source or drain is connected to a source side of the first transistor;

a fourth transistor of which a first of a source or drain is connected to a source side of the first transistor and of which a second of a source or drain is connected to an output side of the output-side inverter circuit;

a first capacitive element of which a first end is connected to a gate side of the first transistor and a second end is connected to an input side of the output-side inverter circuit, and

a correction circuit to correct gate voltage of the first and second transistors;

wherein the correction circuit is configured to set a correction voltage of the first transistor or a voltage corresponding to the correction voltage of the first transistor, for a gate of the first transistor, as an offset voltage to the first transistor, to correct for a threshold voltage in the first transistor, and

wherein the correction circuit also sets a correction voltage of the second transistor or a voltage corresponding to the correction voltage of the second transistor, for a gate of the second transistor, as an offset voltage to the second transistor.

2. The drive circuit according to claim 1 , wherein the correction circuit further comprises a fifth transistor of which a first of a source or drain is connected to a gate side of the first transistor and of which a second of the source or drain is connected to a drain side of the second transistor.

3. The drive circuit according to claim 1 , wherein the correction circuit further comprises:

a sixth transistor of which a first of a source or drain is connected to a gate side of the second transistor and of which a second of a source or drain is connected to a source side of the second transistor;

a seventh transistor of which a first of a source or drain is connected to a source side of the second transistor and of which a second of the source or drain is connected to an output side of the output-side inverter circuit; and

a second capacitive element of which a first end is connected to a gate side of the second transistor and a second end is connected to an input side of the output-side inverter circuit.

4. The drive circuit according to claim 3 , wherein the correction circuit further comprises an eighth transistor of which a first of a source or drain is connected to a gate side of the second transistor and whose source or drain which is not connected to the gate side of the second transistor is connected to a drain side of the first transistor.

5. A display device comprising:

a display section including a plurality of scan lines disposed in rows, a plurality of signal lines disposed in columns, and a plurality of pixels disposed in a matrix; and

a drive section for driving the pixels,

wherein the drive section has a plurality of drive circuits provided for the plurality of scan lines in a one-to-one corresponding manner,

the drive circuit has an input-side inverter circuit and an output-side inverter circuit connected to each other in series and inserted between a high-voltage line and a low-voltage line, and

the output-side inverter circuit includes:

a first transistor whose drain is connected to a high-voltage line side and whose source is connected to an output side of the output-side inverter circuit,

a second transistor whose drain is connected to a low-voltage line side and whose source is connected to an output side of the output-side inverter circuit,

a third transistor of which a first of a source or drain is connected to a gate side of the first transistor and of which a second of the source or drain is connected to a source side of the first transistor;

a fourth transistor of which a first of a source or drain is connected to a source side of the first transistor and of which a second of a source or drain is connected to an output side of the output-side inverter circuit;

a first capacitive element of which a first end is connected to a gate side of the first transistor and a second end is connected to an input side of the output-side inverter circuit, and

a correction circuit to correct gate voltage of the first and second transistors;

wherein the correction circuit is configured to set a correction voltage of the first transistor or a voltage corresponding to the correction voltage of the first transistor, for a gate of the first transistor, as an offset voltage to the first transistor, and

wherein the correction circuit is configured to set a correction voltage of the second transistor or a voltage corresponding to the correction voltage of the second transistor, for a gate of the second transistor as an offset voltage to the second transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2015
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 036106/0355 →