Suspending column addressing in image sensors
View Patent ↗An image sensor includes a two-dimensional array of pixels having multiple column outputs and an output circuit connected to each column output. Each output circuit is configured to operate concurrent sample and read operations. A timing generator outputs a column address sequence that is received by a column decoder that is electrically connected to each output circuit. The timing generator suspends the output of the column address sequence during a sample operation and resumes the output of the column address sequence at the end of the sample operation.
1. A method for reading out an image from an image sensor including a two-dimensional array of pixels having a plurality of column outputs and an output circuit connected to each column output, wherein each output circuit is configured to operate concurrent sample and read operations, the method comprising:
initiating concurrent sample and read operations in each output circuit;
during a first sample operation, suspending a column address sequence, wherein suspending the column address sequence includes holding the column address sequence in a state such that the column address sequence does not address any of the plurality of column outputs for a read operation; and
at or after the completion of the first sample operation, resuming the column address sequence.
2. The method as in claim 1 , further comprising:
during a second sample operation, suspending the column address sequence; and
at or after the completion of the second sample operation, resuming the column address sequence.
3. The method as in claim 2 , wherein the column address sequence is suspended during the first sample operation for a predetermined first number of clock periods.
4. The method as in claim 3 , wherein the column address sequence is suspended during the second sample operation for a predetermined second number of clock periods.
5. The method as in claim 4 , wherein the predetermined first and second numbers of clock periods are the same.
6. The method as in claim 4 , wherein the predetermined first
7. The method as in claim 1 , further comprising selectively storing at least a portion of pixel data output from the output circuits. and second numbers of clock periods are different.