Field effect transistor having multiple pinch off voltages
View Patent ↗A compound field effect transistor having multiple pinch-off voltages, comprising first and second field effect transistors, each field effect transistor comprising a semiconductor layer, the semiconductor layer having an electrically conducting layer therein. An ohmic contact layer on the semiconductor layer, a source and a drain on the ohmic contact layer, at least one gate on the semiconductor layer between source and drain, at least one gate of the first transistor and one gate of the second transistor being matched gates, each gate having the same effective thickness of electrically conducting layer beneath it, but the gates having different gate lengths.
1. A method for manufacture of a compound field effect transistor comprising the steps of:
providing first and second semiconductor layers each semiconductor layer having an electrically conducting layer therein;
providing an ohmic contact layer on each of the semiconductor layers; providing a source and a drain on each ohmic contact layer; providing a mask on the ohmic contact layers; providing a pattern on the mask, the pattern comprising a first via extending through the mask to the ohmic contact layer between the source and the drain of a first transistor and a second via extending through the mask to the ohmic contact layer between the source and drain of a second transistor;
etching through the ohmic contact layer to the semiconductor layer;
depositing first and second gates on the ohmic contact layers through the vias, the vias being arranged such that the first and second gates have different gate lengths; and
etching recesses of the same depth in the semiconductor layers through the first and second vias prior to depositing the gates through the vias.
2. A method as claimed in claim 1 , wherein the first and second semiconductor layers are different parts of the same semiconductor layer.
3. A method of manufacture of a field effect transistor comprising the steps of:
providing a semiconductor layer having an electrically conducting layer therein;
providing an ohmic contact layer on the semiconductor layer;
providing a source and a drain on the ohmic layer;
providing a mask on the ohmic contact layer;
providing a plurality of vias extending through the mask to the ohmic contact layer between the source and the drain;
etching through the ohmic contact layer to the semiconductor layer;
depositing a plurality of gates through vias on the semiconductor layer, the vias being arranged such that at least two of the gates have different gate lengths; and
etching a plurality of recesses of the same depth in the semiconductor layer through the vias prior to depositing the gates.