Memory component having write operation with multiple time periods
A memory component includes a memory core, a control transport block to receive a write command from external control lines, and a write control buffer to store the write command for a first time period after the write command is received at the transport block. A data buffer receives data from external data lines, the data to be stored in the memory core in response to the write command, wherein receipt of the data occurs based on a second time period that follows the first time period, such that receipt of the write command and the data are separated by a delay time that includes both the first time period and the second time period. A write mask buffer receives write masking information from an external write mask line. Receipt of the write command and the write masking information are separated by the delay time.
1. A memory system, comprising:
a communication channel coupled to a controller and coupled to a memory device;
the controller to generate control information and data information, including at least two write commands to the memory device followed by another command and then followed by a read command to the memory device, wherein respective data information corresponds to respective control information, the other command is between the at least two write commands and the read command; and
the memory device to receive the control information and the data information in a same order as generated by the controller and to process the read command prior to completing the processing of one of the at least two write commands;
wherein the memory device comprises:
a memory core having dynamic random access memory cells:
a first interface to receive the two write commands, each specifying a write operation;
a first circuit to store a respective write command for a first time period;
a second interface to receive data associated with the respective write operation, wherein receipt of the data occurs based on a second time period, wherein the second time period follows the first time period, such that receipt of the respective write command and the data are separated by a delay time that includes both the first time period and the second time period.
2. A memory component, comprising:
a memory core having dynamic random access memory cells:
a first interface to receive a write command that specifies a write operation;
a first circuit to store the write command for a first time period;
a second interface to receive data associated with the write operation, wherein receipt of the data occurs based on a second time period, wherein the second time period follows the first time period, such that receipt of the write command and the data are separated by a delay time that includes both the first time period and the second time period.
3. The memory component of claim 2 , further comprising:
a multiplexer circuit coupled to the first interface and the first circuit, the multiplexer circuit to selectively apply, to the memory core, a control signal derived from one of an output of the first circuit and an output of the first interface, such that the multiplexer applies the control signal upon receipt of a read command at the first interface.
4. The memory component of claim 2 wherein the second interface is a data buffer to receive the data from external data lines, wherein the data buffer comprises a first data buffer stage to receive the data from the external data lines and a second data buffer stage to receive the data from the first data buffer stage and to provide the data to the memory core.
5. The memory component of claim 2 , further comprising a third interface to receive write masking information from an external write mask line, wherein the write masking information specifies whether to mask portions of the data to be written to the memory core during the write operation, wherein receipt of the write command and the write masking information are separated by the delay time.
6. A memory component comprising:
a memory core including an array of memory cells;
a control transport block to receive a write command from external control lines, wherein the write command specifies a write operation;
a write control buffer coupled to the control transport block, the write control buffer to store the write command for a first time period after the write command is received at the transport block;
a data buffer to receive data from external data lines, the data to be stored in the memory core in response to the write command, wherein receipt of the data occurs based on a second time period, wherein the second time period follows the first time period, such that receipt of the write command and the data are separated by a delay time that includes both the first time period and the second time period; and
a write mask buffer to receive write masking information from an external write mask line, wherein the write masking information specifies whether to mask portions of the data to be written to the memory core during the write operation, wherein receipt of the write command and the write masking information are separated by the delay time.
7. The memory component of claim 6 , further comprising:
a multiplexer circuit coupled to the write control buffer, the control transport block and the memory core, the multiplexer circuit to apply a delayed version of the write command to the memory core in response to the write command being received at the control transport block, and the multiplexer circuit to apply a non-delayed version of read control information to the memory core in response to a read command being received at the control transport block.
8. The memory component of claim 6 , wherein the array of memory cells is an array of dynamic random access memory cells.
9. The memory component of claim 6 , wherein the data is stored in the memory core after a retire command is received by the control transport block.
10. The memory component of claim 6 , wherein the delay time corresponds to a read delay time minus a predetermined delay time.
11. The memory component of claim 10 , wherein the predetermined delay time is a channel turnaround time.
12. A method of operation of a memory component that includes a memory core having dynamic random access memory cells, the method comprising:
at a first interface of the memory component, receiving a write command, wherein the write command specifies a write operation;
after receiving the write command, storing the write command for a first time period; and
at a second interface of the memory component, receiving data associated with the write operation, wherein receipt of the data occurs after a second time period transpires, the second time period following the first time period, such that receiving the write command and receiving the data are separated by a delay time that includes both the first time period and the second time period.
13. The method of claim 12 , further comprising:
receiving mask information that indicates whether to mask portions of the data to be written to the memory core during the write operation; and
during the write operation, writing unmasked portions of the data to the memory core, wherein the unmasked portions of the data are bits of the data that are identified by the mask information as not being masked.
14. The method of claim 13 , further comprising:
after receiving the data, storing the data in a write buffer; and
receiving a retire command that indicates writing the unmasked portions of the data in the write buffer to the memory core.
15. The method of claim 12 , wherein storing the write command comprises buffering the write command through a plurality of buffer stages during the first time period.
16. The method of claim 12 , further comprising:
receiving a read command that specifies a read operation;
applying the read command to the memory core to service the read operation; and
after a read delay time, outputting read data corresponding to the read command.
17. The method of claim 16 , wherein the delay time corresponds to the read delay time minus a predetermined delay time.
18. The method of claim 17 , wherein the predetermined delay time is a channel turnaround time.
19. A method of operation of a memory component that includes a memory core having dynamic random access memory cells, the method comprising:
at a first interface of the memory component, receiving a write command, wherein the write command specifies a write operation;
after receiving the write command, storing the write command for a first time period,
at a second interface of the memory component, receiving data associated with the write operation, wherein receipt of the data occurs after a second time period transpires, the second time period following the first time period, such that receiving the write command and receiving the data are separated by a delay time that includes both the first time period and the second time period; and
receiving mask information that indicates whether to mask portions of the data to be written to the memory core during the write operation, wherein receiving the write command and receiving the mask information are separated by the delay time that includes both the first time period and the second time period.
20. The method of claim 19 , further comprising:
during the write operation, writing unmasked portions of the data to the memory core, wherein the unmasked portions of the data are bits of the data that are identified by the mask information as not being masked;
after receiving the data, storing the data in a write buffer; and
receiving a retire command that indicates writing the unmasked portions of the data in the write buffer to the memory core.
21. The method of claim 19 , wherein the delay time corresponds to a read delay time minus a predetermined delay time.
22. The method of claim 21 , further comprising:
receiving a read command that specifies a read operation;
applying the read command to the memory core to service the read operation; and
after the read delay time, outputting read data corresponding to the read command.
23. The method of claim 21 , wherein the predetermined delay time is a channel turnaround time.