IP Library Granted Patent US 8,216,934
Granted Patent B2
US 8,216,934 · App. 12/976,089 · Granted Jul 10, 2012

Semiconductor device suitable for a stacked structure

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Quick Facts
Patent No.
US 8,216,934
App. No.
12/976,089
Granted
Jul 10, 2012
Kind
B2
Abstract

A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.

Claims (18)

1. A method of manufacturing a semiconductor device comprising:

preparing a semiconductor substrate having an integrated circuit unit and an electrode pad electrically coupled to the integrated circuit unit above a first surface;

reducing a thickness of the semiconductor substrate by grinding a second surface opposite to the first surface;

forming a hole that extends from the second surface to the electrode pad, such that the hole exposes the surface of the electrode pad at a bottom of the hole;

forming an insulating film to cover an inner surface of the hole;

forming an opening by selectively removing a part of the insulating film extending parallel to the surface of the electrode pad and covering the surface of the electrode pad at the bottom of the hole such that a part of the surface of the electrode pad exposed by the hole is exposed by the opening while the remaining part of the surface of the electrode pad is covered by the remaining art of the insulation film extending parallel to the surface of the electrode pad; and

filling a metal material in the hole to couple to the electrode pad.

2. The method according to claim 1 , wherein, in the process of forming the hole, the electrode pad serves as an etching stopper layer.

3. The method according to claim 1 , wherein the hole has a first diameter in an upper part of the hole and a second diameter in a bottom part of the hole, the second diameter is smaller than the first diameter.

4. The method according to claim 3 , wherein the hole has a taper structure.

5. The method according to claim 3 , wherein the hole has a conic structure.

6. The method according to claim 1 , further forming a metal layer above the insulating film such that the metal layer is electrically coupled to the electrode pad.

7. The method according to claim 6 , wherein the metal layer consists of a titanium layer and a copper layer.

8. The method according to claim 1 , wherein the metal material consists of copper, gold and nickel.

9. The method according to claim 1 , wherein the process of filling the metal material includes forming a stud bump electrically coupled to the electrode pad.

10. The method according to claim 9 , wherein the stud bump consists of gold.

11. The method according to claim 1 , wherein said forming of said opening is conducted by providing a mask pattern on the second surface.

12. The method according to claim 11 , wherein the mask pattern comprises a dry film.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2015
From: FUJITSU SEMICONDUCTOR LIMITED
To: SOCIONEXT INC.
Reel/Frame 035508/0337 →