IP Library Granted Patent US 8,754,988
Granted Patent B2
US 8,754,988 · App. 12/976,729 · Granted Jun 17, 2014

Blur detection with local sharpness map

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Quick Facts
Patent No.
US 8,754,988
App. No.
12/976,729
Granted
Jun 17, 2014
Kind
B2
Abstract

A single-ended blur detection probe and method with a local sharpness map for analyzing a video image sequence uses two sets of edge filters, one for “fast edges” and the other for “slow edges.” Each set of edge filters includes a horizontal bandpass filter, a vertical bandpass filter and a pair of orthogonal diagonal filters where the frequency response of the fast edge filters overlap the frequency response of the slow edge filters. The video image sequence is input to each filter of each set, and the output absolute values are combined with weighting factors to produce a slow edge weighted sum array and a fast edge weighted sum arra. The respective weighted sum arrays are then decimated to produce a slow edge decimated array and a fast edge decimated array. The ratio of the maximum difference value between the decimated arrays and the maximum value from the fast edge decimated array, weighted by an appropriate factor, produces a localized maximum sharpness value, the log of which produces a dimensionless blur value.

Claims (62)

1. A probe for determining image blurriness comprising:

a first set of edge filters configured to detect fast edges within an input image to produce a plurality of fast edge filter outputs;

a second set of edge filters configured to detect slow edges within the input image to produce a plurality of slow edge filter outputs;

a first summation circuit configured to combine the fast edge filter outputs to produce a fast edge filter output array;

a second summation circuit configured to combine the slow edge filter outputs to produce a slow edge filter output array;

circuitry configured to decimate the fast edge and the slow edge filter output arrays separately to produce a decimated fast edge filter array and a decimated slow edge filter array; and

circuitry configured to process the respective decimated fast edge and slow edge filter arrays to generate a localized maximum sharpness value as a measure of the blurriness of the input image.

2. The probe as recited in claim 1 wherein the first and second sets of edge filters each comprise:

a horizontal edge filter having the input image as an input and producing a horizontal filter output;

a vertical edge filter having the input image as an input and producing a vertical filter output;

a first diagonal edge filter having the input image as an input and producing a first diagonal filter output; and

a second diagonal edge filter orthogonal to the first diagonal edge filter having the input image as an input and producing a second diagonal filter output.

3. The probe as recited in claim 2 wherein each edge filter comprises a filter having a bandpass characteristic along a principal direction and a lowpass filter characteristic along an orthogonal direction to the principal direction, bandpass frequencies for the first set of edge filters overlapping bandpass frequencies for the second set of edge filters.

4. The probe as recited in claim 3 wherein each edge filter comprises a filter having a filter kernel of 0s, 1s and 2s that define the bandpass characteristic along the principal direction and the lowpass filter characteristic along the orthogonal direction.

5. The probe as recited in claim 2 wherein the first and second summation circuits each comprise:

a first summation block configured to combine the horizontal edge filter output with the vertical edge filter output to produce a first edge filter summation output;

a second summation block configured to combine the first diagonal edge filter output with the second diagonal edge filter output to produce a second edge filter summation output;

circuitry configured to weight each of the first and second edge filter summation outputs to produce respective weighted sum edge filter outputs; and

a third summation block configured to combine the respective weighted sum edge filter outputs to produce the fast edge and slow edge filter arrays respectively.

6. The probe as recited in claim 1 wherein the decimating circuitry comprises:

a lowpass filter for each of the fast edge and slow edge filter arrays having the respective edge filter array as an input to produce respective filtered edge filter arrays; and

a decimator configured to decimate each of the filtered edge filter arrays to produce the respective decimated edge filter arrays.

7. The probe as recited in claim 6 wherein the decimating circuitry further comprises a crop block configured to crop the edges of the respective fast edge and slow edge filter arrays prior to input to the respective lowpass filters.

8. The probe as recited in claim 1 wherein the processing circuitry comprises:

a difference block configured to combine the decimated fast edge and decimated slow edge filter arrays to produce a difference filter array;

circuitry configured to generate a ratio between the difference filter array and the decimated fast edge filter array to produce the localized maximized sharpness value.

9. The probe as recited in claim 8 wherein the ratio generating circuitry comprises:

a first maximum value block configured to obtain a maximum of the decimated fast edge filter array and a second maximum value block configured to obtain a maximum of the difference filter array; and

a divider configured to divide the maximum of the difference filter array by the maximum of the fast edge filter array to produce the localized maximized sharpness value.

10. The probe as recited in claim 9 wherein the ratio generating circuitry further comprises a multiplier configured to multiply the output from the divider by a sharpness factor to produce the localized maximized sharpness value.

11. The probe as recited in claim 10 wherein the ratio generating circuitry further comprises a logarithmic block configured to obtain the log of the output from the multiplier to produce the localized maximized sharpness value as a dimensionless value.

12. The probe as recited in claim 2 further comprising circuitry configured to disable the horizontal and vertical edge filter outputs of each of the first and second sets of edge filters so the edge filter outputs from the first and second sets of edge filters reflect only the filter outputs from respective diagonal edge filter pairs.

13. The probe as recited in claim 1 wherein the processing circuitry comprises:

a difference block having as inputs the fast edge and slow edge decimated filter output arrays to produce a difference filter output array;

circuitry configured to generate from the difference filter array and a sharpness ratio localized markers configured to superimpose on the input image to indicate where the sharpest edges occur within the input image.

14. The probe as recited in claim 13 wherein the generating circuitry comprises:

a threshold generator having the difference filter output array and a sharpness ratio as inputs and producing a threshold value as an output;

a comparator having the difference filter output array and the threshold value as inputs and producing the localized markers as output when the difference filter output array exceeds the threshold value.

15. The probe as recited in claim 2 further comprising:

a third summation circuit configured to combine the horizontal and vertical edge filter outputs for the first set of edge filters to produce a first fast edge filter output array;

a fourth summation circuit configured to combine the first and second diagonal edge filter outputs for the first set of edge filters to produce a second fast edge filter output array;

circuitry configured to decimate the first and second fast edge filter output arrays to produce decimated first and second fast edge filter output arrays; and

a combination block configured to compare a ratio of the first and second fast edge filters with a tiling threshold to produce a tiling flag indicative of block artifacts within the input image.

16. The probe as recited in claim 15 further comprising circuitry configured to disable the horizontal and vertical edge filter outputs of each of the first and second sets of edge filters in response to the tiling flag so the edge filter outputs from the first and second sets of edge filters reflect only the filter outputs from respective diagonal edge filter pairs.

17. The probe as recited in claim 1 further comprising:

a comparison block configured to compare the localized maximum sharpness value with a sharpness threshold; and

circuitry configured to generate an up conversion flag when the sharpness threshold is less than the localized maximum sharpness value for a predetermined period of time, indicating the input image was upconverted from a lower resolution image.

18. A method of determining image blurriness comprising the steps of:

filtering an input image with a first set of edge filters configured to detect fast edges in the input image to produce a plurality of fast edge filter outputs;

filtering the input image with a second set of edge filters configured to detect slow edges in the input image to produce a plurality of slow edge filter outputs;

combining the fast edge filter outputs to produce a fast edge filter output array by way of a first summation circuit;

combining the slow edge filter outputs to produce a slow edge filter output array by way of a second summation circuit;

decimating the fast edge and the slow edge filter output arrays separately to produce a decimated fast edge filter array and a decimated slow edge filter array; and

processing the respective decimated fast edge and slow edge filter arrays to generate a localized maximum sharpness value as a measure of the blurriness of the input image.

19. The method as recited in claim 18 further comprising the steps of:

obtaining a difference between the fast edge and slow edge decimated filter output arrays to produce a difference filter output array;

generating from the difference filter output array and a sharpness ratio localized markers for superimposing on the input image to indicate where the sharpest edges occur within the input image.

20. The method as recited in claim 18 further comprising the steps of:

combining horizontal and vertical edge filter outputs for the first set of edge filters to produce a first fast edge filter output array;

combining first and second diagonal edge filter outputs for the first set of edge filters to produce a second fast edge filter output array;

decimating the first and second fast edge filter output arrays to produce decimated first and second fast edge filter output arrays; and

comparing a ratio of the first and second fast edge filters with a tiling threshold to produce a tiling flag indicative of block artifacts within the input image.

Assignments (7)
SECURITY INTEREST Recorded Jun 9, 2025
From: INEOQUEST TECHNOLOGIES, LLC; PROJECT GIANTS, LLC
To: FORTRESS CREDIT CORP.
Reel/Frame 071493/0030 →
CORRECTIVE ASSIGNMENT TO CORRECT THE MISSING PROPERTY AND GRANTOR NAME OF PROJECT GIANTS. LLC PREVIOUSLY RECORDED AT REEL: 054089 FRAME: 0786. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 1, 2021
From: PROJECT GIANTS, LLC
To: FORTRESS CREDIT CORP., AS AGENT
Reel/Frame 056442/0845 →
RELEASE OF SECURITY INTEREST Recorded Oct 16, 2020
From: SILICON VALLEY BANK
To: PROJECT GIANTS, LLC
Reel/Frame 054090/0934 →
SECURITY INTEREST Recorded Oct 15, 2020
From: PROJECT GIANT, LLC
To: FORTRESS CREDIT CORP., AS AGENT
Reel/Frame 054089/0786 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 25, 2019
From: TEKTRONIX, INC.
To: PROJECT GIANTS, LLC
Reel/Frame 049870/0073 →
PATENT SECURITY AGREEMENT Recorded Jul 22, 2019
From: PROJECT GIANTS, LLC
To: SILICON VALLEY BANK
Reel/Frame 049819/0702 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 4, 2013
From: BAKER, DANIEL G.
To: TEKTRONIX, INC.
Reel/Frame 030544/0862 →