Memory controller and associated control method
View Patent ↗A memory controller and an associated controlling method are provided. The memory controller is connected to a memory module, and includes a FIFO buffer for receiving valid data outputted from the memory module, a write pointer for indicating written data stored in the FIFO buffer, and a read pointer for indicating read data stored in the FIFO buffer. According to the controlling method, during a CAS latency of the memory module after a read command is generated, the value of the write pointer is controlled to have the same value as that of the read pointer.
1. A memory controller, coupled to a memory module, comprising:
a command generator that generates a read command and provides the read command to the memory module;
a first-in-first-out (FIFO) buffer that stores data received from the memory module according to a data strobe signal generated by the memory module in response to receiving the read command;
a write pointer that generates a write count according to the data strobe signal, the write count being associated with a position of the stored data in the FIFO buffer;
a read pointer that maintains a read count according to a number of times that data in the FIFO buffer is read, the read count being associated with a position of the read data in the FIFO buffer; and
a pointer calibration unit that sets the write count to be same as the read count after the read command is generated and before the memory module outputs the data.
2. The memory controller as recited in claim 1 , wherein the memory module is a double-data-rate (DDR) memory module.
3. The memory controller as recited in claim 1 , wherein the read pointer increments the read count by one every time the data in the FIFO buffer is read.
4. The memory controller as recited in claim 1 , wherein the FIFO buffer is a ring buffer, and the read pointer and the write pointer are counters.
5. The memory controller as recited in claim 1 , wherein the pointer calibration unit compares the read count and the write count, and updates the read count of the read pointer to the write count of the write counter when the read count and the write count are different.
6. A method for controlling a memory controller, the memory controller coupled to a memory module, the method comprising:
providing information of a latency of the memory module;
generating a read command that is provided to the memory module;
storing data received from the memory module into a first-in-first-out (FIFO) buffer of the memory controller; and
setting a write count to be same as a read count during the latency of the memory module when the read command is generated, the write count being associated with a position of written data in the FIFO buffer, the read count being associated with a position of read data in the FIFO buffer.
7. The method as recited in claim 6 , wherein the memory module is a double-data-rate (DDR) memory module.
8. The method as recited in claim 6 , wherein the latency of the memory module is associated with a column address strobe signal (CAS) latency.
9. The method as recited in claim 6 , further comprising:
updating the write count according to a data strobe signal of the memory module.
10. The method as recited in claim 6 , further comprising:
updating the read count according to a number of times that the data in the FIFO buffer is read.
11. The method as recited in claim 6 , wherein the FIFO buffer is a ring buffer.
12. A method for controlling a memory controller, the memory controller coupled to a memory module, the method comprising:
providing information of a latency of the memory module;
determining whether a read command is generated by a command generator of the memory controller;
comparing a read count with a write count when the read command is generated, the write count being associated with a position of written data in a first-in-first-out (FIFO) buffer of the memory controller, the read count being associated with a position of read data in the FIFO buffer; and
setting the write count to be same as the read count during the latency when the write count differs from the read count.
13. The method as recited in claim 12 , wherein the memory module is a double-data-rate (DDR) memory module.
14. The method as recited in claim 12 , further comprising:
updating the write count according to a data strobe signal of the memory module.
15. The method as recited in claim 12 , further comprising:
updating the read count according to a number of times that data in the FIFO buffer is read.
16. The method as recited in claim 12 , wherein the FIFO buffer is a ring buffer.