Baseboard management controller and memory error detection method of computing device utilized thereby

1. A memory error detection method of a computing device using a baseboard management controller (BMC) of the computing device, the method comprising:

adjusting an operating frequency of a microprocessor of the BMC according to a bus frequency of a platform environment control interface (PECI) bus;

controlling the microprocessor to communicate with a processor of the computing device based on the operating frequency of the microprocessor;

reading data of a state register of the processor when the microprocessor receives an interrupt signal generated by the processor due to an internal error of the processor;

determining whether the internal error is a multiple-bit error of a memory of the computing device according to the read data; and

recording error information of the multiple-bit error in a storage system of the BMC upon the condition that the internal error is the multiple-bit error.

2. The method according to claim 1 , wherein the processor is electronically connected with the BMC through the PECI bus.

3. The method according to claim 1 , wherein the interrupt signal is sent to the microprocessor through a general purpose input output interface of the processor.

4. The method according to claim 1 , wherein the error information comprise serial numbers of the memory, an error type of the multiple-bit error, and time information when the multiple-bit error occurs.

5. The method according to claim 1 , further comprising:

acquiring the error information from the storage system when the computing device is rebooted due to the multiple-bit error;

detecting the memory of which the multiple-bit error has occurred according to the error information; and

modifying a command of a control register of the processor to control the processor not to access the memory of which the multiple-bit error has occurred.

6. A computing device, comprising:

at least one processor;

at least one memory;

a baseboard management controller (BMC) comprising a microprocessor and a storage system; and

one or more programs stored in the storage system and being executable by the microprocessor, the one or more programs comprising:

an adjustment module operable to adjust an operating frequency of the microprocessor according to a bus frequency of a platform environment control interface (PECI) bus, and control the microprocessor to communicate with the processor based on the operating frequency;

a detection module operable to read data of a state register of the processor when the microprocessor receives an interrupt signal generated by the processor due to an internal error of the processor, and determine whether the internal error is a multiple-bit error of the memory according to the read data; and

a recording module operable to record error information of the multiple-bit error in the storage system upon the condition that the internal error is the multiple-bit error.

7. The computing device according to claim 6 , wherein the processor is electronically connected with the BMC through the PECI bus.

8. The computing device according to claim 6 , wherein the interrupt signal is sent to the microprocessor through a general purpose input output interface of the processor.

9. The computing device according to claim 6 , wherein the error information comprise serial numbers of the memory, an error type of the multiple-bit error, and time information when the multiple-bit error occurs.

10. The computing device according to claim 6 , wherein the computing device comprises a basic input output system (BIOS) operable to:

acquire the error information from the storage system when the computing device is rebooted due to the multiple-bit error;

detect the memory of which the multiple-bit error has occurred according to the error information; and

modify a command of a control register of the processor to control the processor not to access the memory of which the multiple-bit error has occurred.

11. A non-transitory computer readable storage medium storing a set of instructions, the set of instructions capable of being executed by a microprocessor of a baseboard management controller (BMC) of a computing device, causes the computing device to perform a memory error detection method using the BMC, the method comprising:

adjusting an operating frequency of the microprocessor according to a bus frequency of a platform environment control interface (PECI) bus;

controlling the microprocessor to communicate with a processor of the computing device based on the operating frequency of the microprocessor;

reading data of a state register of the processor when the microprocessor receives an interrupt signal generated by the processor due to an internal error of the processor;

determining whether the internal error is a multiple-bit error of a memory of the computing device according to the read data; and

recording error information of the multiple-bit error in a storage system of the BMC upon the condition that the internal error is the multiple-bit error.

12. The storage medium as claimed in claim 11 , wherein the processor is electronically connected with the BMC through the PECI bus.

13. The storage medium as claimed in claim 11 , wherein the interrupt signal is sent to the microprocessor through a general purpose input output interface of the processor.

14. The storage medium as claimed in claim 11 , wherein the error information comprise serial numbers of the memory, an error type of the multiple-bit error, and time information when the multiple-bit error occurs.

15. The storage medium as claimed in claim 11 , wherein the method further comprises:

acquiring the error information from the storage system when the computing device is rebooted due to the multiple-bit error;

detecting the memory of which the multiple-bit error has occurred according to the error information; and

modifying a command of a control register of the processor to control the processor not to access the memory of which the multiple-bit error has occurred.