Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling
View Patent ↗A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”.
1. In a nonvolatile memory have memory cells accessible by word lines, said memory cells individually having threshold voltages each programmable into one of a first set of threshold voltage bands in a threshold window partitioned by a first set of reference thresholds, the first set of threshold voltage bands being coded by a first set of bits, a method of reading a current group of memory cells on a current word line, comprising:
sensing the programmed threshold voltages of an adjacent group of memory cells on an adjacent word line to determine coupling levels due to charges stored in neighboring memory cells on individual memory cells in the current group on the current word line, the coupling levels including a substantially zero coupling level corresponding to substantially zero charges from neighboring memory cells;
sensing the current group of memory cells by permuting a current word line voltage selected from the first set of reference thresholds and an adjacent word line voltage selected from a set of bias voltages obtained as a function of different associated coupling levels;
obtaining the first set of bits when the bias voltage during the permutation corresponds to the substantially zero coupling level;
obtaining a second set of bits when the bias voltage during the permutation corresponds to other than the substantially zero coupling level; and wherein:
said permuting a current word line voltage selected from the first set of reference thresholds and an adjacent word line voltage selected from a set of bias voltages obtained as a function of different associated coupling levels is to iterate through each of the reference thresholds in the first set on the current word line after selecting a next one in the set of bias voltages on the adjacent word line until the set of bias voltages is exhausted.
2. The method as in claim 1 , further comprising:
processing a read code word from the first and second sets of bits with an error correcting code (ECC) decoder to obtain an error-corrected code word for the memory cells of the current group.
3. The method as in claim 1 , wherein:
said first set of bits is a grey code.
4. The method as in claim 1 , wherein:
said second set of bits is a grey code.
5. The method as in claim 1 , wherein:
the nonvolatile memory is organized with a NAND architecture.
6. The method as in claim 1 , wherein:
the first set of bits and the second set of bits are generated during a reading scheme in which the coupling effects of charges from neighboring cells are compensated for during sensing.
7. A nonvolatile memory, comprising:
memory cells accessible by word lines, said memory cells individually having threshold voltages each programmable into one of a first set of threshold voltage bands in a threshold window partitioned by a first set of reference thresholds, the first set of threshold voltage bands being coded by a first set of bits;
sensing circuits to sense a current group of memory cells in parallel on a current word line;
said sensing circuits sensing the programmed threshold voltages of an adjacent group of memory cells on an adjacent word line to determine coupling levels due to charges stored in neighboring memory cells on individual memory cells in the current group on the current word line, the coupling levels including a substantially zero coupling level corresponding to substantially zero charges from neighboring memory cells;
said sensing circuits sensing the current group of memory cells by permuting a current word line voltage selected from the first set of reference thresholds and an adjacent word line voltage selected from a set of bias voltages obtained as a function of different associated coupling levels,
so as to obtain the first set of bits when the bias voltage during the permutation corresponds to the substantially zero coupling level, and
to obtain a second set of bits when the bias voltage during the permutation corresponds to other than the substantially zero coupling level; and wherein:
said sensing circuits sensing the current group of memory cells by permuting a current word line voltage selected from the first set of reference thresholds and an adjacent word line voltage selected from a set of bias voltages obtained as a function of different associated coupling levels is to iterate through each of the reference thresholds in the first set on the current word line after selecting a next one in the set of bias voltages on the adjacent word line until the set of bias voltages is exhausted.
8. The nonvolatile memory as in claim 7 , further comprising:
an error correcting code (ECC) decoder to process a read code word from the first and second sets of bits to obtain an error-corrected code word for the memory cells of the current group.
9. The nonvolatile memory as in claim 7 , wherein:
said first set of bits is a grey code.
10. The nonvolatile memory as in claim 7 , wherein:
said second set of bits is a grey code.
11. The nonvolatile memory as in claim 7 , wherein:
the nonvolatile memory is organized with a NAND architecture.
12. The nonvolatile memory as in claim 7 , wherein:
the first set of bits and the second set of bits are generated during a reading scheme in which the coupling effects of charges from neighboring cells are compensated for during sensing.