Coefficient boost multiply accumulate unit

1. A multiply accumulate (MAC) unit, comprising:

an adder having first and second adder inputs and an adder output;

an accumulation register configured to store a value equal to a sum of a current input to the adder and a preceding output of the adder previously stored in the accumulation register, wherein the accumulation register comprises an output and an input coupled to the adder output;

a bit-shift element having an input coupled to the output of the accumulation register;

a feedback path that includes an arithmetic element disposed thereon, wherein the feedback path has a first end, which branches off a path connecting the output of the accumulation register and the input of the bit-shift element, and has a second end, which is coupled to the second adder input; and

a switch disposed between the arithmetic element and the second adder input, wherein the switch has a first input terminal coupled to the arithmetic element, a second input terminal coupled to another data path, and an output terminal coupled to the second adder input,

wherein the switch selectively couples the arithmetic element and the another data path to the second adder input.

2. The MAC unit of claim 1 , further comprising:

a multiplier comprising: a first multiplier input to receive a first input vector, a second multiplier input to receive a second input vector, and a multiplier output to provide an output vector to the first adder input, wherein the output vector is a product of the first and second input vectors.

3. The MAC unit of claim 2 , wherein the arithmetic element on the feedback path operates on an output value from the accumulation register and provides an arithmetically operated on value to the second adder input.

4. The MAC unit of claim 1 , wherein the arithmetic element is a bit shift element to bit-shift a multi-bit value.

5. The MAC unit of claim 4 , wherein the bit shift element is configured to uni-directionally bit shift the multi-bit value.

6. The MAC unit of claim 1 , wherein the arithmetic element is a multiplier.

7. The MAC unit of claim 1 , wherein the arithmetic element is a divider.

8. The MAC unit of claim 1 , wherein the first end of the feedback path is coupled to a branch point located directly at the output of the accumulation register.

9. A multiply accumulate (MAC) unit, comprising:

an adder having first and second adder inputs and an adder output;

an accumulation register configured to store a value equal to a sum of a current input to the adder and a preceding output of the adder previously stored in the accumulation register, wherein the accumulation register comprises an output and an input coupled to the adder output;

a bit-shift element having an input coupled to the output of the accumulation register; and

a feedback path that includes an arithmetic element disposed thereon, wherein the feedback path has a first end, which branches off a path connecting the output of the accumulation register and the input of the bit-shift element, and has a second end, which is coupled to the second adder input,

wherein the arithmetic element is a bit shift element to bit-shift a multi-bit value, and

wherein the arithmetic element is a bit shift element configured to bi-directionally shift the multi-bit output value.

10. A multiply accumulate (MAC) unit, comprising:

an accumulate unit comprising: an adder having a first adder input terminal and an adder output terminal, and an accumulation register having an input coupled to the adder output terminal, wherein the accumulation register is configured to store a value equal to a sum of a current input to the adder and a preceding output of the adder previously stored in the accumulation register; and

an arithmetic element disposed on a feedback path coupling an output of the accumulation register to a second adder input terminal of the adder, wherein the feedback path has a first end coupled to a branch point located directly at the output of the accumulation register and has a second end coupled to the second adder input terminal,

wherein the arithmetic element is a bit shift element to bit-shift a multi-bit output value provided by the accumulation unit, and

wherein the bit shift element is configured to bi-directionally bit shift the multi-bit output value provided the accumulation unit.

11. The MAC unit of claim 10 , wherein the arithmetic element is a multiplier.

12. The MAC unit of claim 10 , wherein the arithmetic element is a divider.

13. The MAC unit of claim 12 , further comprising:

a bit-shift element downstream of the accumulate unit.

14. The MAC unit of claim 10 , further comprising:

a multiplier comprising: first and second multiplier input terminals and a multiplier output terminal, wherein the multiplier output terminal is coupled to the first adder input terminal.

15. The MAC unit of claim 14 , further comprising:

a bit-shift element operably coupled between the multiplier and the accumulate unit.

16. A multiply accumulate (MAC) unit, comprising:

an accumulate unit comprising: an adder having a first adder input terminal and an adder output terminal, and an accumulation register having an input coupled to the adder output terminal, wherein the accumulation register is configured to store a value equal to a sum of a current input to the adder and a preceding output of the adder previously stored in the accumulation register;

an arithmetic element disposed on a feedback path coupling an output of the accumulation register to a second adder input terminal of the adder, wherein the feedback path has a first end coupled to a branch point located directly at the output of the accumulation register and has a second end coupled to the second adder input terminal;

a multiplier comprising first and second multiplier input terminals and a multiplier output terminal, wherein the multiplier output terminal is coupled to the first adder input terminal; and

a switch disposed between the arithmetic element and the second adder input, wherein the switch has a first input terminal coupled the arithmetic element, a second input terminal coupled to another data path, and an output terminal coupled to the second adder input terminal;

wherein the switch selectively couples the arithmetic element and the another data path to the second adder input terminal.