Controlling plating stub reflections in a chip package

1. A method of controlling plating stub reflections in a chip package, the method comprising:

determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount;

based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width for an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate, wherein selecting a line width of an open-ended plating stub based on the performance characteristics of the bond wire includes:

generating, by the resonance optimizer, an eye pattern based on the performance characteristics of the bond wire and the selected line width of the open-ended plating stub;

determining, by the resonance optimizer, if the eye pattern is acceptable;

if the eye pattern is acceptable, using, by the resonance optimizer, the selected line width of the open-ended plating stub in the design of the signal traces; and

if the eye pattern is not acceptable, selecting, by the resonance optimizer, a new line width for the open-ended plating stub in the design of the signal traces; and

generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width.

2. The method of claim 1 , wherein the performance characteristics of the bond wire includes an impedance of the bond wire.

3. The method of claim 1 , wherein the selected line width of the open-ended plating stub is between one half and one fourth of a line width of the bond wire.

4. An apparatus for controlling plating stub reflections in a chip package, the apparatus comprising a computer processor and a computer memory operatively coupled to the computer processor, the computer memory having disposed within it computer program instructions, which when executed, cause the computer processor to perform steps of:

determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount;

based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width of an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate, wherein selecting a line width of an open-ended plating stub based on the performance characteristics of the bond wire includes:

generating, by the resonance optimizer, an eye pattern based on the performance characteristics of the bond wire and the selected line width of the open-ended plating stub;

determining, by the resonance optimizer, if the eye pattern is acceptable;

if the eye pattern is acceptable, using, by the resonance optimizer, the selected line width of the open-ended plating stub in the design of the signal traces; and

if the eye pattern is not acceptable, selecting, by the resonance optimizer, a new line width for the open-ended plating stub in the design of the signal traces; and

generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width.

5. The apparatus of claim 4 , wherein the performance characteristics of the bond wire includes an impedance of the bond wire.

6. The apparatus of claim 4 , wherein the selected line width of the open-ended plating stub is between one half and one fourth of a line width of the bond wire.

7. A computer readable storage medium for controlling plating stub reflections in a chip package ,the computer readable storage medium comprising computer program instructions which, when executed, causes a computer to carry out the steps of:

determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount;

based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width of an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate, wherein selecting a line width of an open-ended plating stub based on the performance characteristics of the bond wire includes:

generating, by the resonance optimizer, an eye pattern based on the performance characteristics of the bond wire and the selected line width of the open-ended plating stub;

determining, by the resonance optimizer, if the eye pattern is acceptable;

if the eye pattern is acceptable, using, by the resonance optimizer, the selected line width of the open-ended plating stub in the design of the signal traces; and

if the eye pattern is not acceptable, selecting, by the resonance optimizer, a new line width for the open-ended plating stub in the design of the signal traces; and

generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width.

8. The computer readable storage medium of claim 7 , wherein the performance characteristics of the bond wire includes an impedance of the bond wire.

9. The computer readable storage medium of claim 7 , wherein the selected line width of the open-ended plating stub is between one half and one fourth of a line width of the bond wire.

10. A multi-layer substrate for controlling plating stub reflections in a chip package, comprising:

a first outer layer providing a chip mounting location, a signal interconnect spaced from the chip mounting location, a signal trace extending from near the chip mounting location to the signal interconnect, and an open-ended plating stub extending from the signal interconnect;

wherein the line width of the open-ended plating stub is determined by:

determining, by a resonance optimizer, performance characteristics of a bond wire, the bond wire connecting a chip to a substrate of a semiconductor chip mount;

based on the performance characteristics of the bond wire, selecting, by the resonance optimizer, a line width of an open-ended plating stub, the open-ended plating stub extending from a signal interconnect of the substrate to a periphery of the substrate, wherein selecting a line width of an open-ended plating stub based on the performance characteristics of the bond wire includes:

generating, by the resonance optimizer, an eye pattern based on the performance characteristics of the bond wire and the selected line width of the open-ended plating stub;

determining, by the resonance optimizer, if the eye pattern is acceptable;

if the eye pattern is acceptable, using, by the resonance optimizer, the selected line width of the open-ended plating stub in the design of the signal traces; and

if the eye pattern is not acceptable, selecting, by the resonance optimizer, a new line width for the open-ended plating stub in the design of the signal traces; and

generating, by the resonance optimizer, a design of signal traces for the substrate, the signal traces including the open-ended plating stub with the selected line width.

11. The multi-layer substrate of claim 10 , wherein the selected line width of the open-ended plating stub is between one half and one fourth of a line width of the bond wire.