Method for implementing the π/8 gate in a genus=1 ising system
View Patent ↗Disclosed herein is a protocol that enables the π/8-gate in chiral topological superconductors in which superconducting stiffness λ has been suppressed. The protocol enables a topologically protected π/8-gate in any pure Ising system that can be fabricated into genus=1 surface. By adding the π/8-gate to previously known techniques, a design for universal topologically protected quantum computation which may be implemented using rather conventional materials may be obtained.
1. A method for implementing a π/8 gate in a genus=1 Ising system, the method comprising:
providing a standard Ising qubit in a dynamical topology changing device (DTC);
filling with a state X during a first time τ ∈[0, ⅔];
measuring a charge |1> or |ψ> along a boundary of the DTC; and
recording the measurement classically.
2. The method of claim 1 , wherein the filling occurs within the DTC.
3. The method of claim 1 , wherein the filling occurs within the DTC by applying gates to realize a state X 2DEG.
4. The method of claim 1 , wherein the filling occurs within the DTC by applying gates to realize a state X 2DEG, except near a certain point p.
5. The method of claim 4 , wherein the charge |1> or |ψ> is measured along a boundary surrounding the point p.
6. The method of claim 1 , further comprising unfilling a portion of the DTC near a (1, −2)-curve during a time τ ∈[⅔, 1].
7. The method of claim 6 , wherein the unfilling is accomplished by applying gates on the DTC.