Delay-locked-loop circuit, semiconductor device and memory system having the delay-locked-loop circuit

1. A delay-locked-loop (DLL) circuit, comprising:

a first DLL configured to adjust a delay time of an external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency; and

a second DLL configured to adjust the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.

2. The DLL circuit as claimed in claim 1 , wherein the first DLL stores locking information of the first internal clock signal having a low frequency and the second DLL stores locking information of the second internal clock signal having a high frequency, and during a subsequent operation the DLL circuit generates an internal clock signal synchronized with the external clock signal using the locking information of the first internal clock signal and the locking information of the second internal clock signal.

3. The DLL circuit as claimed in claim 1 , wherein the first DLL and the second DLL operate in response to a mode register set signal.

4. The DLL circuit as claimed in claim 1 , wherein the locking information of the first internal clock signal is a delay amount of a delay line of the first DLL, and the locking information of the second internal clock signal is a delay amount of a delay line of the second DLL.

5. The DLL circuit as claimed in claim 1 , further comprising a selecting circuit configured to select one of the first internal clock signal and the second internal clock signal to generate an internal clock signal in response to a mode register set signal.

6. The DLL circuit as claimed in claim 1 , wherein the first DLL comprises:

a phase detector configured to compare the external clock signal and a feedback signal to generate an up signal and a down signal;

a delay control circuit configured to store locking information for a clock signal having the low frequency, and to generate delay control signals based on the up signal and the down signal; and

a delay line configured to delay the external clock signal to generate the first internal clock signal in response to the delay control signals.

7. The DLL circuit as claimed in claim 6 , wherein the delay control circuit operates when the external clock signal has a low frequency, and does not operate when the external clock signal has a high frequency.

8. The DLL circuit as claimed in claim 6 , wherein the first DLL further comprises a replica path that delays the first internal clock signal to generate the feedback clock signal.

9. The DLL circuit as claimed in claim 1 , wherein the second DLL comprises:

a phase detector configured to compare the external clock signal and a feedback signal to generate an up signal and a down signal;

a delay control circuit configured to store locking information for a clock signal having the high frequency, and to generate delay control signals based on the up signal and the down signal; and

a delay line configured to delay the external clock signal to generate the second internal clock signal in response to the delay control signals.

10. The DLL circuit as claimed in claim 9 , wherein the delay control circuit operates when the external clock signal has a high frequency, and does not operate when the external clock signal has a low frequency.

11. A semiconductor device, comprising:

a delay-locked-loop (DLL) circuit configured to generate an internal clock signal synchronized with an external clock signal; and

an internal circuit configured to operate in response to the internal clock signal, wherein the DLL circuit includes:

a first DLL configured to adjust a delay time of the external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency; and

a second DLL configured to adjust the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.

12. The semiconductor device as claimed in claim 11 , wherein the semiconductor device is a semiconductor memory device.

13. The semiconductor device as claimed in claim 12 , wherein the internal circuit is an output circuit of the semiconductor memory device.

14. A memory system, comprising:

a memory controller; and

a semiconductor memory device configured to transmit data to or receive data from the memory controller,

wherein the semiconductor memory device includes:

a delay-locked-loop (DLL) circuit configured to generate an internal clock signal synchronized with an external clock signal; and

an internal circuit configured to operate in response to the internal clock signal, wherein the DLL circuit, includes:

a first DLL configured to adjust a delay time of the external clock signal to generate a first internal clock signal synchronized with the external clock signal when the external clock signal has a low frequency; and

a second DLL configured to adjust the delay time of the external clock signal to generate a second internal clock signal synchronized with the external clock signal when the external clock signal has a high frequency.

15. The memory system claimed in claim 14 , wherein the first DLL stores locking information of the first internal clock signal having a low frequency and the second DLL stores locking information of the second internal clock signal having a high frequency, and during a subsequent operation the DLL circuit generates an internal clock signal synchronized with the external clock signal using the locking information of the first internal clock signal and the locking information of the second internal clock signal.