IP Library Granted Patent US 8,253,617
Granted Patent B2
US 8,253,617 · App. 12/982,027 · Granted Aug 28, 2012

Analog-to-digital conversion in pixel arrays

Assignee: Cmosis NV
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Quick Facts
Patent No.
US 8,253,617
App. No.
12/982,027
Granted
Aug 28, 2012
Kind
B2
Abstract

An analog-to-digital converter (ADC) generates an output digital value equivalent to the difference between two analog signal values. The ADC receives a first analog signal level, a second analog signal level and a ramp signal. A counter is operable to count in a single direction. A control stage is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal. A digital value accumulated by the counter during a period when it is enabled forms the output. The ADC can perform the conversion during a single cycle of the ramp signal. The counter can be loaded with a starting digital value representing an exposure level accumulated during a previous exposure period. Techniques are described for reducing the conversion time.

Claims (14)

1. An analog-to-digital converter for generating an output digital value equivalent to the difference between two analog signal values comprising:

at least one input for receiving a first analog signal level and a second analog signal level;

an input for receiving a ramp signal;

a counter which is operable to count in a single direction;

a control stage which is arranged to enable the counter based on a comparison of the ramp signal with the first analog signal and the second analog signal;

an output for outputting a value accumulated by the counter during a period when it is enabled;

wherein the control stage is arranged to accumulate digital signal values for elements of an image over multiple exposure periods and is further arranged to begin the counter at a starting digital value which represents a previously accumulated exposure level for an element of the image.

2. An analog-to-digital converter according to claim 1 further comprising a connection to a memory, and wherein the control stage is further arranged to:

read a digital value from the memory at the beginning of a processing operation for an exposure period, which digital value represents a previously accumulated exposure level of an element of the image;

output a digital value to the memory at the end of a processing operation for an exposure period, which digital value represents a new accumulated exposure level of the element of the image.

3. An analog-to-digital converter according to claim 1 wherein the control stage is arranged to determine whether to enable the counter based on the accumulated exposure level for an element of the image.

4. An analog-to-digital converter according to claim 3 wherein the control stage is arranged to make an independent determination of whether to enable the counter for each element of the image.

5. An analog-to-digital converter according to claim 1 wherein the control stage is arranged to use a dedicated counter to accumulate the digital signal value for a particular element of the image across the multiple exposure periods.

6. An analog-to-digital converter according to claim 1 wherein the pixel array is operable to perform time delay integration (TDI) and each exposure period is a TDI cycle.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2010
From: BOGAERTS, JAN
To: CMOSIS NV
Reel/Frame 025559/0145 →
Priority Claims (1)
GB 0806427.1 · Apr 9, 2008 · national
Continuity (2)
Continuation 12388590 · Feb 19, 2009
Related Publication 20110095929A1 · Apr 28, 2011