PLASMA TREATMENT ON SEMICONDUCTOR WAFERS
A semiconductor package and method of forming the same is described. The semiconductor package is formed from a semiconductor die cut from a semiconductor wafer that has a passivation layer. The semiconductor wafer is exposed to ionized gas causing the passivation layer to roughen. The semiconductor wafer is cut to form a plurality of semiconductor dies each with a roughened passivation layer. The plurality of semiconductor dies are placed on an adhesive layer to form a reconstituted wafer, and an encapsulation layer is formed enclosing the adhesive layer and the plurality of semiconductor dies. The passivation layer is removed and the semiconductor package formed includes electrical contacts for establishing electrical connections external to the semiconductor package.
1 . A method comprising:
exposing a passivation layer on a semiconductor wafer to ionized gas causing an exposed surface of the passivation layer to roughen;
cutting the semiconductor wafer into a plurality of semiconductor dies; and
affixing the plurality of semiconductor dies to an adhesion layer for forming a packaged semiconductor device, the exposed surface of the passivation layer being in contact with the adhesion layer.
2 . The method of claim 1 , wherein the ionized gas is produced in an ionization chamber.
3 . The method of claim 1 , wherein the ionized gas is any one of oxygen and tetrafluoride gases.
4 . The method of claim 1 , wherein the passivation layer is any one of silicon nitride, silicon dioxide, and oxynitride.
5 . The method of claim 1 , further comprising:
forming an encapsulation layer enclosing the adhesion layer and the plurality of semiconductor dies affixed to the adhesion layer.
6 . The method of claim 1 , wherein the ionized gas is produced using plasma etching.
7 . The method of claim 6 , wherein the plasma etching is one of reactive-ion etching and inductive coupled plasma etching.
8 . The method of claim 1 , wherein the adhesion layer comprises adhesive tape.
9 . An integrated chip packaging system comprising:
a cutting device configured to cut a semiconductor wafer into a plurality of semiconductor dies;
an ionization chamber configured to expose a passivation surface of the semiconductor wafer to ionized gas; and
an affixing device configured to affix the plurality of semiconductor dies to an adhesion layer of a reconstituted wafer, the passivation surface of the plurality of semiconductor dies being in contact with the adhesion layer.
10 . The integrated chip packaging system of claim 9 , wherein the ionized gas is any one of oxygen and tetrafluoride gases.
11 . The integrated chip packaging system of claim 9 , wherein the passivation surface is part of a passivation layer comprised of any one of silicon nitride, silicon dioxide, and oxynitride.
12 . The integrated chip packaging system of claim 9 , wherein the ionized gas is produced using plasma etching.
13 . The integrated chip packaging system of claim 12 , wherein the plasma etching is one of reactive-ion etching and inductive coupled plasma etching.
14 . The integrated chip packaging system of claim 11 , further comprising:
a planarization device configured to remove the passivation layer.
15 . The integrated chip packaging system of claim 14 , wherein the passivation layer is removed using one of chemical mechanical planarization (“CMP”) and plasma etching.
16 . A semiconductor package comprising:
a semiconductor die;
a passivation layer coupled to one side of the semiconductor die, the passivation layer having been subjected to ionized gas and forming a roughened surface on the passivation layer; and
an encapsulation layer enclosing at least two sides of the semiconductor die and leaving exposed the roughened surface of the passivation layer.
17 . The semiconductor package of claim 16 , wherein the ionized gas is one of oxygen and tetrafluoride.
18 . The semiconductor package of claim 16 , wherein the passivation layer is any one of silicon nitride, silicon dioxide, and oxynitride.
19 . The semiconductor package of claim 16 , further comprising:
electrical contacts coupled to the semiconductor die, the electrical contacts being configured to establish an electrical connection external to the semiconductor package.
20 . The semiconductor package of claim 19 , wherein the electrical contacts include solder balls.