Error protection method, TDC module, CTDC module, all-digital phase-locked loop, and calibration method thereof
View Patent ↗An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) includes: retrieving a digital code received by the TDC decoder; retrieving a cycle code received by the TDC decoder; performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.
1. An error protection method for a time-to-digital converter (TDC) decoder of an all-digital phase-locked loop (ADPLL) comprises:
retrieving a digital code received by the TDC decoder;
retrieving a cycle code received by the TDC decoder;
performing an exclusive-or operation on a first predetermined bit of the digital code and a second predetermined bit of the cycle code for generating an error protection code; and
using the error protection code to fix errors within the cycle code by adding the error protection code into the cycle code and shifting the cycle code by a third predetermined number of bits.
2. The error protection method of claim 1 wherein the digital code has 2 m bits and the cycle code has m bits; wherein m is a positive integer.
3. The error protection method of claim 2 wherein performing the exclusive-or operation on the first predetermined bit of the digital code and the second predetermined bit of the cycle code for generating the error protection code comprises:
performing the exclusive-or operation on a last bit of the digital code and a first bit of the cycle code for generating the error protection code.
4. The error protection method of claim 3 wherein performing the exclusive-or operation on the last bit of the digital code and the first bit of the cycle code for generating the error protection code comprises:
performing the exclusive-or operation on the last bit of the digital code and the first bit of the cycle code for generating the error protection code according to:
err_protect=XOR( D[ 2 m −1], C[ 0])
wherein D indicates the digital code; C indicates the cycle code;
err_protect indicates the error protection code;
wherein adding the error protection code into the cycle code and raising the cycle code by the third predetermined number of bits comprises:
adding the error protection code into the cycle code and raising the cycle code by m bits according to
TDC[0:2·( m− 1)+1]=( C[ 0:( m− 1)]+err_protect) *2 m +output1[0:( m− 1)]
wherein TDC indicates an output signal of the TDC decoder of the ADPLL; output 1 indicates an decoding signal of the TDC decoder for indicating how many bits are 0 or how many bits are 1 in the digital code D.