Generic bus de-multiplexer/port expander with inherent bus signals as selectors
A circuit comprising: a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line and at least one signal line; and a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal.
1. A circuit comprising:
a device determiner configured to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line; and at least one signal line; and
a device router configured to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal,
wherein the device determiner comprises:
a counter configured to receive a first clock signal via a clock line as a reset input and to receive a second clock signal via at least one of: at least one control line and at least one signal line as the clock input; and
a decoder configured to receive an output from the counter and generate a latch activation signal when a determined number of second clock signal cycles is reached.
2. The circuit as claimed in claim 1 , wherein the device determiner further comprises a latch configured to latch the device selection signal via the remainder of the at least one control line and at least one signal line dependent on the latch activation signal.
3. The circuit as claimed in claim 2 , wherein the latch is further configured concatenate at least two latched device selection signals over at least two second clock signal cycles; wherein the device router is configured to in the second mode of operation, route signals from the at least one of: at least one control line and at least one signal line to at least one device dependent on the concatenated device selection signal.
4. The circuit as claimed in claim 1 , wherein the device router comprises a demultiplexer configured to receive the device selection signal as a selector input; the main clock signal as the clocked input; and the at least one of: at least one control line and at least one signal line as the signal input.
5. A router comprising the circuit as claimed in claim 1 .
6. An integrated circuit comprising the circuit as claimed in claim 1 .
7. A method of routing signals, the method comprising:
configuring a device determiner to, in a first mode of operation, receive a device selection signal via at least one of: at least one control line; and at least one signal line; and
configuring a device router to, in a second mode of operation, route signals between the at least one of: at least one control line and at least one signal line and at least one device dependent on the device selection signal,
wherein the device determiner comprises:
a counter configured to receive a first clock signal via a clock line as a reset input and to receive a second clock signal via at least one of: at least one control line and at least one signal line as the clock input; and
a decoder configured to receive an output from the counter and generate a latch activation signal when a determined number of second clock signal cycles is reached.
8. The method as claimed in claim 7 , wherein the device determiner further comprises a latch configured to latch the device selection signal via the remainder of the at least one control line and at least one signal line dependent on the latch activation signal.
9. The method as claimed in claim 8 , wherein the latch is further configured concatenate at least two latched device selection signals over at least two second clock signal cycles; wherein the device router is configured to, in the second mode of operation, route signals from the at least one of: at least one control line and at least one signal line to at least one device dependent on the concatenated device selection signal.
10. The method as claimed in claim 7 , wherein the device router comprises a demultiplexer configured to receive the device selection signal as a selector input; the main clock signal as the clocked input; and the at least one of: at least one control line and at least one signal line as the signal input.
11. The method as claimed in claim 7 , performed within a router.
12. The method as claimed in claim 7 , performed within an integrated circuit.