Semiconductor device and method of manufacturing the same
View Patent ↗In a well region, an irregular structure is formed in a gate width direction, and a gate electrode is formed in concave portions and on top surfaces of convex portions via an insulating film. Upper and lower source regions are formed on one side of the gate electrode in a gate length direction, and upper and lower drain regions are formed on the other side thereof. By thus forming the lower source and drain regions in the source and drain regions, current concentration occurring in an upper portion of a channel region, which is generated as the gate length becomes shorter, may be suppressed and a current may be allowed to flow uniformly in the entire channel region, and hence an effective gate width is made wider owing to the irregular structure formed in the well region. Accordingly, an on-resistance of a semiconductor device is reduced to enhance driving performance.
1. A semiconductor device, comprising:
a semiconductor substrate having an epitaxial layer thereon;
a first conductivity type well region comprising a lower well region in the semiconductor substrate and an upper well region in the epitaxial layer, the first conductivity type well region having irregularities therein in a gate width direction;
a gate electrode formed in the irregularities via an insulating film;
a second conductivity type upper source region in the upper well region on a first side of the gate electrode in an irregular longitudinal direction;
a second conductivity type lower source region in the upper well region and the lower well region below and in contact with the second conductivity type upper source region;
a second conductivity type upper drain region in the upper well region on a second side of the gate electrode in the irregular longitudinal direction; and
a second conductivity type lower drain region in the upper well region and the lower well region below and in contact with the second conductivity type upper drain region.
2. A semiconductor device according to claim 1 , wherein regions of the second conductivity type upper drain region and the second conductivity type lower drain region adjacent to the gate electrode have a low impurity concentration.
3. A semiconductor device according to claim 1 , wherein a conductivity-determining dopant concentration in the lower source region and the lower drain region is greater than a conductivity-determining dopant concentration in the upper well region.
4. A semiconductor device according to claim 3 further comprising low concentration regions between the upper and lower drain regions and the gate electrode, wherein the low concentration regions have a conductivity-determining dopant concentration that is less than the upper and lower drain regions.
5. A semiconductor device according to claim 1 , wherein the irregularities of the first conductivity type well region comprise concave portions and convex portions in a surface of the well region.
6. A semiconductor device according to claim 5 further comprising a channel region in the well region and extending below the concave portions and convex portions, the channel region having a upper portion adjacent to the upper source and drain regions and a lower portion adjacent to the lower source and drain regions, wherein a current concentration in upper portion is less than a current concentration in the lower portion.