IP Library › Patent Application 12983815
Patent Application
App. No. 12/983,815

DECOMPRESSOR/PRPG FOR APPLYING PSEUDO-RANDOM AND DETERMINISTIC TEST PATTERNS

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Quick Facts
Patent No.
US None
App. No.
12/983,815
Abstract

A novel decompressor/PRPG on a microchip performs both pseudo-random test pattern generation and decompression of deterministic test patterns for a circuit-under-test on the chip. The decompressor/PRPG has two phases of operation. In a pseudo-random phase, the decompressor/PRPG generates pseudo-random test patterns that are applied to scan chains within the circuit-under test. In a deterministic phase, compressed deterministic test patterns from an external tester are applied to the decompressor/PRPG. The patterns are decompressed as they are clocked through the decompressor/PRPG into the scan chains. The decompressor/PRPG thus provides much better fault coverage than a simple PRPG, but without the cost of a complete set of fully-specified deterministic test patterns.

Claims (12)

1 .- 33 . (canceled)

34 . A method for applying test patterns to scan chains of a circuit-under test, the method comprising:

in a first of multiple modes of operation,

decompressing bits of a compressed deterministic test pattern into a decompressed deterministic test pattern as the bits of the compressed deterministic test pattern are received; and

outputting the decompressed deterministic test pattern to the scan chains of the circuit-under test.

35 . The method of claim 34 , further comprising:

in a second of the multiple modes of operation,

generating a set of pseudo-random test patterns; and

outputting the pseudo-random test patterns to the scan chains of the circuit-under-test.

36 . A system, comprising:

means for, in a first of multiple modes of operation, decompressing bits of a compressed deterministic test pattern into a decompressed deterministic test pattern as the bits of the compressed deterministic test pattern are received and outputting the decompressed deterministic test pattern to scan chains of a circuit-under test; and

means for, in a second of the multiple modes of operation, generating a set of pseudo-random test patterns and outputting the pseudo-random test patterns to the scan chains of the circuit-under-test.