Method of fabricating high-voltage semiconductor device

1. A method of fabricating a high-voltage semiconductor device, the method comprising:

providing a semiconductor layer;

forming a plurality of trenches in the semiconductor layer to define a plurality of pillars of a first conductivity type in the semiconductor layer between adjacent trenches, wherein the trenches extend from a top surface of the semiconductor layer toward a bottom surface of the semiconductor layer;

forming a charge compensation layer of a second conductivity type over at least sidewalls of each trench to a predetermined thickness thereby forming a groove in each trench;

substantially filling each groove with a charge compensation plug of the first conductivity type; and

forming a plurality of wells of the second conductivity type in the semiconductor layer such that each well forms a PN junction with a corresponding charge compensation plug and with two pillars adjacent to the corresponding charge compensation plug and contacts a corresponding charge compensation layer on opposing sidewalls of the two pillars.

2. The method of claim 1 , wherein the providing of the semiconductor layer comprises forming a first epitaxial layer on a substrate,

wherein the trenches are formed in the first epitaxial layer.

3. The method of claim 1 , wherein the forming of the charge compensation layer comprises:

forming a second epitaxial layer in the trenches to the predetermined thickness by performing a CVD (chemical vapor deposition) process using a layer-forming gas; and

diffusing impurity ions into the second epitaxial layer by performing an annealing process in a gas atmosphere containing the impurity ions.

4. The method of claim 1 , wherein the forming of the charge compensation layer comprises;

forming a second epitaxial layer in the trenches to the predetermined thickness by performing a CVD process and doping in-situ using a layer-forming gas containing the impurity ions.

5. The method of claim 1 , wherein the charge compensation layer also extends over a bottom surface of each trench.

6. The method of claim 1 , wherein the plurality of trenches are formed by etching the semiconductor layer using a plasma dry etching process.

7. The method of claim 1 , wherein the forming of the charge compensation plug comprises forming a third epitaxial layer by performing a CVD process and doping in-situ using a layer-forming gas containing the impurity ions.

8. The method of claim 1 , wherein the forming of the charge compensation layer is performed by forming a second epitaxial layer on the semiconductor layer including the sidewalls and bottom surface of the trenches while doping first impurity ions in-situ by means of a first CVD process using a first layer-forming gas containing the first impurity ions,

wherein the forming of the charge compensation plug is performed by forming a third epitaxial layer on the second epitaxial layer while doping second impurity ions in-situ by means of a second CVD process using a second layer-forming gas containing the second impurity ions,

the method further comprising planarizing the second epitaxial layer and the third epitaxial layer until the top surface of the semiconductor layer is exposed.

9. The method of claim 1 , further comprising forming a plurality of source regions of the first conductivity type in the wells adjacent to the top surface of the semiconductor layer.

10. The method of claim 9 , further comprising forming a plurality of gate stacks each laterally extending over a top surface of a corresponding well and a top surface of a corresponding pillar such that an underlying region of the corresponding well forms a channel between a source region and the corresponding pillar, wherein each gate stack includes a gate insulating layer and a gate electrode layer.

11. The method of claim 1 , wherein the sum of the amount of charges in the pillars and in the charge compensation plugs is substantially equal to the amount of charges in the charge compensation layer.

12. The method of claim 1 , wherein the pillars and the charge compensation plugs have substantially the same first dopant concentration, and the charge compensation layer has a second dopant concentration.

13. The method of claim 1 , further comprising performing a thermal diffusion process of impurities in the charge compensation layer and the charge compensation plugs after forming the charge compensation plugs.

14. A method of fabricating a high-voltage semiconductor device, the method comprising:

providing a semiconductor layer;

forming a plurality of trenches in the semiconductor layer, each adjacent pair of trenches defining a mesa region therebetween;

forming a charge compensation impurity layer of a second conductivity type vertically extending in each mesa region along each trench sidewall such that a remaining portion of each mesa region between every two adjacent charge compensation impurity layers forms a pillar of a first conductivity type;

substantially filling each trench with a charge compensation plug of the first conductivity type; and

forming a plurality of wells of the second conductivity type in the semiconductor layer such that each well forms a PN junction with a corresponding charge compensation plug and with two pillars adjacent to the corresponding charge compensation plug and contacts a corresponding charge compensation layer on opposing sidewalls of the two pillars.

15. The method of claim 14 , wherein the providing of the semiconductor layer comprises forming a first epitaxial layer on a substrate,

wherein the trenches are formed in the first epitaxial layer.

16. The method of claim 14 , wherein the forming of the charge compensation impurity layer is performed by means of an impurity diffusion process using a gas containing an impurity element.

17. The method of claim 14 , wherein the plurality of trenches are formed by etching the semiconductor layer using a plasma dry etching process.

18. The method of claim 14 , wherein the forming of the charge compensation plugs comprises forming a second epitaxial layer by performing a CVD process and doping in-situ using a layer-forming gas containing the impurity ions.

19. The method of claim 18 , further comprising planarizing the second epitaxial layer until the top surface of the semiconductor layer is exposed, after forming the second epitaxial layer.

20. The method of claim 14 , wherein the pillars and the charge compensation plugs have substantially the same first dopant concentration, and the charge compensation impurity layer has a second dopant concentration, the second dopant concentration being higher than the first dopant concentration.

21. The method of claim 14 , wherein the sum of the amount of charges in the pillars and in the charge compensation plugs is substantially equal to the amount of charges in the charge compensation impurity layer.

22. The method of claim 21 , further comprising forming a plurality of source regions of the first conductivity type in the wells adjacent to the top surface of the semiconductor layer.

23. The method of claim 22 , further comprising forming a plurality of gate stacks each laterally extending over a top surface of a corresponding well and a top surface of a corresponding pillar such that an underlying region of the corresponding well forms a channel between a source region and the corresponding pillar, wherein each gate stack includes a gate insulating layer and a gate electrode layer.

24. The method of claim 14 , further comprising performing a thermal diffusion process of impurities in the charge compensation layer and the charge compensation plugs after forming the charge compensation plugs.

25. The method of claim 24 , wherein due to the thermal diffusion process, the impurities in the charge compensation layer and the charge compensation plug diffuse out such that the boundaries of the charge compensation layer and the charge compensation plug become blurred.

26. The method of claim 13 , wherein due to the thermal diffusion process, the impurities in the charge compensation layer and the charge compensation plug diffuse out such that the boundaries of the charge compensation layer and the charge compensation plug become blurred.