IP Library Granted Patent US 8,621,235
Granted Patent B2
US 8,621,235 · App. 12/985,898 · Granted Dec 31, 2013

Secure pin entry device

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Quick Facts
Patent No.
US 8,621,235
App. No.
12/985,898
Granted
Dec 31, 2013
Kind
B2
Abstract

A secure PIN entry device including a PIN entry assembly operative to receive a PIN from a user, a PIN entry prompter operative when actuated to prompt a user to enter a PIN via the PIN entry assembly, a PIN entry prompt security check enabled controller operative to prevent operation of the PIN entry prompter unless a predetermined security check has been successfully completed and security check functionality operative to check at least part of the PIN entry device for the presence of an unauthorized PIN eavesdropping element thereat and to provide an output to the PIN entry prompt security check enabled controller indicating whether the predetermined security check has been successfully completed.

Claims (31)

1. A secure PIN entry device comprising:

a PIN entry assembly operative to receive a PIN from a user, said PIN entry assembly including a first plurality of key pads and a second plurality of bug sensing floods, electrically insulated from and adjacent to said first plurality of key pads; and

security check circuitry operative to check at least part of said PIN entry device for the presence of an unauthorized PIN eavesdropping element thereat and to provide an output indicating whether a predetermined security check has been successfully completed, said security check functionality comprising bug detection circuitry for checking said at least part of said PIN entry device for the presence of an unauthorized PIN eavesdropping element thereat, said bug detection circuitry including:

an electric field generator for simultaneously generating an electromagnetic field at least some of said first plurality of key pads and said second plurality of bug sensing floods; and

mutual capacitance sensing circuitry operative to sense mutual capacitance between some of said first plurality of key pads and said second plurality of bug sensing floods and others of said first plurality of key pads and said second plurality of bug sensing floods resulting from said electromagnetic field thereat, said mutual capacitance sensing circuitry being operative in a key entry detection mode using autotuning functionality and in a security scan mode not using autotuning functionality.

2. The secure PIN entry device according to claim 1 and wherein said security check functionality is operative, in the event of discovery of a bug, to at least one of provide an output alarm and disable one or more functions of the PIN entry device.

3. The secure PIN entry device according to claim 1 and also comprising case open detection functionality.

4. The secure PIN entry device according to claim 3 and wherein said case open detection functionality is operative, in the event of a case open condition being detected, to at least one of provide an output alarm and disable one or more functions of the PIN entry device.

5. The secure PIN device according to claim 1 and wherein said mutual capacitance sensing functionality, when operative in said security scan mode, combines changes in sensed mutual capacitance of a plurality of elements of said secure PIN entry device which exceed a predetermined threshold in order to ascertain whether a bug is present.

6. The secure PIN entry device according to claim 3 and also comprising case-open switches and wherein said mutual capacitance sensing functionality is applied to elements of said case-open switches.

7. The secure PIN entry device according to claim 1 and wherein at least one of said second plurality of bug sensing floods comprises a mesh.

8. A secure data entry device comprising:

a data entry assembly operative to receive data from a user, said data entry assembly including multiple elements including a first plurality of key pads and a second plurality of bug sensing floods, electrically insulated from and adjacent to said first plurality of key pads;

a data entry security check enabled controller operative to prevent receipt of said data by said data entry assembly unless a predetermined security check has been successfully completed; and

mutual capacitance security check circuitry operative to check at least part of said data entry device for the presence of an unauthorized data eavesdropping element thereat by sensing mutual capacitance of at least one of said bug sensing floods with at least another element of said data entry assembly and to provide an output to said data entry security check enabled controller indicating whether said predetermined security check has been successfully completed, said mutual capacitance security check circuitry forming part of mutual capacitance sensing functionality which is operative in a key entry detection mode using autotuning functionality and in a security scan mode not using autotuning functionality.

9. The secure data entry device according to claim 8 and wherein said mutual capacitance sensing functionality, when operative in a security scan mode, combines changes in sensed mutual capacitance of a plurality of elements of said secure data entry device which exceed a predetermined threshold in order to ascertain whether a bug is present.

10. The secure data entry device according to claim 8 and wherein said mutual capacitance security check functionality comprises;

a signal generator simultaneously applying a signal to at least some of said first plurality of said key pads;

a signal receiver receiving signals from at least some of said second plurality of bug sensing floods; and

a difference value calculator operative to calculate a difference value for each flood from which a signal is received vis-à-vis a suitably temperature corrected baseline for each of the floods.

11. The secure data entry device according to claim 10 and also comprising an absolute value sum comparison circuit which compares a sum of the absolute values of said difference values with a suitable threshold.

12. The secure data entry device according to claim 8 and wherein said mutual capacitance security check functionality comprises;

a signal generator simultaneously applying a signal to at least some of said first plurality of said key pads;

a signal receiver receiving signals from at least others of said first plurality of key pads; and

a difference value calculator operative to calculate a difference value for each of said others of said first plurality of key pads vis-à-vis a suitably temperature corrected baseline for each of the floods.

13. The secure data entry device according to claim 12 and also comprising an absolute value sum comparison circuit which compares a sum of the absolute values of said difference values with a suitable threshold.

14. The secure data entry device according to claim 8 and wherein said mutual capacitance security check functionality comprises;

a signal generator simultaneously applying a signal to at least some of said second plurality of said bug sensing floods;

a signal receiver receiving signals from at least some of said first plurality of key pads; and

a difference value calculator operative to calculate a difference value for each of said some of said first plurality of key pads vis-à-vis a suitably temperature corrected baseline for each of the some of said first plurality of key pads.

15. The secure data entry device according to claim 14 and also comprising an absolute value sum comparison circuit which compares a sum of the absolute values of said difference values with a suitable threshold.

Assignments (10)
ASSIGNMENT OF SECURITY INTEREST IN PATENT COLLATERAL RECORDED AT R/F 046920-0784 Recorded Apr 28, 2025
From: UBS AG, STAMFORD BRANCH, AS SUCCESSOR TO CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS ASSIGNOR
To: BARCLAYS BANK PLC, AS ASSIGNEE
Reel/Frame 071095/0667 →
AFFIDAVIT TO AFFIRM THE RELEASE OF SECURITY INTEREST IN PATENTS AND TRADEMARKS EFFECTIVE AUGUST 20, 2018 Recorded Apr 14, 2025
From: JPMORGAN CHASE BANK, N.A.
To: VERIFONE, INC.
Reel/Frame 072942/0674 →
RELEASE OF SECURITY INTEREST RECORDED AT REEL/FRAME 46920/0817 Recorded May 10, 2019
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: VERIFONE SYSTEMS, INC.; VERIFONE, INC.; HYPERCOM CORPORATION
Reel/Frame 049150/0190 →
FIRST LIEN PATENT SECURITY AGREEMENT Recorded Aug 23, 2018
From: VERIFONE, INC.; HYPERCOM CORPORATION
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH AS COLLATERAL AGENT
Reel/Frame 046920/0784 →
SECOND LIEN PATENT SECURITY AGREEMENT Recorded Aug 23, 2018
From: VERIFONE, INC.; HYPERCOM CORPORATION
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH AS COLLATERAL AGENT
Reel/Frame 046920/0817 →
RELEASE (R033282F0757) Recorded Aug 21, 2018
From: JPMORGAN CHASE BANK, N.A.
To: VERIFONE, INC.; HYPERCOM CORPORATION; GLOBAL BAY MOBILE TECHNOLOGIES, INC.
Reel/Frame 046864/0909 →
CHANGE OF ADDRESS Recorded May 30, 2016
From: VERIFONE, INC.
To: VERIFONE, INC.
Reel/Frame 038845/0718 →
SECURITY INTEREST Recorded Jul 9, 2014
From: VERIFONE, INC.; HYPERCOM CORPORATION; GLOBAL BAY MOBILE TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 033282/0757 →
SECURITY INTEREST Recorded Jan 24, 2012
From: VERIFONE, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 027580/0337 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2011
From: BARROWMAN, JOHN HENRY; MANCHESTER, DOUGLAS L.
To: VERIFONE, INC.
Reel/Frame 026092/0818 →