Stacked structure and stacked method for three-dimensional chip

1. A stacked structure of a three-dimensional (3D) chip, comprising:

a function chip which is at least capable of performing arithmetic computation;

an input/output (I/O) chip which is stacked below the function chip and performs input/output operations of the 3D chip to an external world; and

a first memory chip, stacked between the function chip and the I/O chip,

wherein the function chip and the I/O chip communicate by a serial transmission mode, the function chip and the I/O chip respectively convert data into a serial signal format by serial interfaces, and vertically transmit the data to each other through a signal line.

2. The stacked structure of the 3D chip as claimed in claim 1 , wherein serial transmission mode comprises a synchronous serial transmission mode or an asynchronous serial transmission mode.

3. The stacked structure of the 3D chip as claimed in claim 1 , wherein the function chip and the first memory chip are stacked according to a face-to-face stacking method.

4. The stacked structure of the 3D chip as claimed in claim 1 , wherein the function chip and the first memory chip are stacked according to a face-to-back stacking method.

5. The stacked structure of the 3D chip as claimed in claim 1 , further comprising:

a second memory chip, stacked between the first memory chip and the I/O chip.

6. The stacked structure of the 3D chip as claimed in claim 5 , wherein the first memory chip and the second memory chip are stacked according to a face-to-back stacking method.

7. The stacked structure of the 3D chip as claimed in claim 5 , wherein the I/O chip transmits power to the function chip through a plurality of through silicon vias (TSVs).

8. The stacked structure of the 3D chip as claimed in claim 7 , wherein the I/O chip further transmits power to the first and the second memory chips through the TSVs.

9. The stacked structure of the 3D chip as claimed in claim 5 , wherein the function chip accesses the first and the second memory chips through a plurality of TSVs.

10. The stacked structure of the 3D chip as claimed in claim 5 , wherein the function chip, the I/O chip and the first and the second memory chips are packaged according to a flip chip package technique.

11. The stacked structure of the 3D chip as claimed in claim 10 , further comprising:

a heat sink, disposed above the 3D chip for dissipating heat of the 3D chip.

12. The stacked structure of the 3D chip as claimed in claim 10 , further comprising:

a plurality of bumps, electrically connected to the I/O chip to serve as external pins of the 3D chip.

13. The stacked structure of the 3D chip as claimed in claim 5 , wherein a logic chip is formed by the function chip and the I/O chip,

wherein the logic chip is a processor, and the first and the second memory chips are respectively a static random access memory or a dynamic random access memory.

14. A stacked method for a three-dimensional chip, comprising:

functionally dividing a logic chip into a function chip and an I/O chip and providing the function chip and the I/O chip, wherein the logic chip is at least capable of performing arithmetic computation and logic operations through the function chip;

stacking the function chip above the I/O chip, wherein the I/O chip performs input/output operations to an external world; and

stacking at least one memory chip between the function chip and the I/O chip, wherein the memory chip communicate to the function chip and the I/O chip,

wherein the function chip and the I/O chip communicate by a serial transmission mode, the function chip and the I/O chip respectively convert data into a serial signal fonnat by serial interfaces, and vertically transmit the data to each other through a signal line.