Mechanisms for efficient intra-die/intra-chip collective messaging
Mechanism of efficient intra-die collective processing across the nodelets with separate shared memory coherency domains is provided. An integrated circuit die may include a hardware collective unit implemented on the integrated circuit die. A plurality of cores on the integrated circuit die is grouped into a plurality of shared memory coherence domains. Each of the plurality of shared memory coherence domains is connected to the collective unit for performing collective operations between the plurality of shared memory coherence domains.
1. A method for intra-die collective messaging, comprising: a plurality of shared memory coherence domains on an integrated circuit die communicating with one another using a hardware collective unit implemented on the integrated circuit die, the hardware collective unit comprising a plurality of local buffers, a local buffer in the plurality of local buffers allocated for each of the plurality of shared memory coherence domains, the hardware collective unit further comprising one or more reduce function units that progressively reduce data in the local buffers received from respective shared memory coherence domains, at least one of the one or more reduce function units interfacing to a network interface, the one or more reduce function units comprising a plurality of ALUs, the hardware collective unit further comprising a plurality of collective unit interfaces, each connecting to a corresponding one of the plurality of shared memory coherence domains, the hardware collective unit further comprising a broadcast logic connecting to the plurality of collective unit interfaces;
configuring said hardware collective unit using an operation control configuration logic associated with the hardware collective unit; and
performing, by the hardware collective unit, a message passing interface collective operation based on data received from the plurality of shared memory coherence domains according to the control configuration logic,
wherein the hardware collective unit combines results from each of the plurality of shared memory coherence domains, and
wherein the step of the plurality of shared memory coherence domains on an integrated circuit die communicating with one another includes writing and reading data to and from corresponding data buffers in the hardware collective unit allocated respectively for the plurality of shared memory coherence domains.
2. The method of claim 1 , further including a plurality of cores in a shared memory coherence domain using shared memory and associated coherence policy to communicate data among the plurality of cores.
3. The method of claim 1 , wherein the step of the plurality of shared memory coherence domains on an integrated circuit die communicating with one another includes individual cores of the plurality of shared memory coherence domains writing and reading data to and from corresponding data buffers in the hardware collective unit allocated respectively for the plurality of shared memory coherence domains.
4. The method of claim 1 , wherein a software application programs the control configuration logic.