Non-volatile memory devices, operating methods thereof and memory systems including the same

1. A nonvolatile memory device which includes a plurality of memory cells that are sequentially arranged in a vertical direction to a substrate, comprising:

a memory cell array including a plurality of word lines connected to the plurality of memory cells; and

a word line driver configured to apply a plurality of word line voltages corresponding to the plurality of word lines, a magnitude of each of the plurality of word line voltages based on a location of a corresponding one of the plurality of word lines.

2. The nonvolatile memory device of claim 1 , wherein each of the plurality of word lines is associated with a different one of a plurality of groups of word lines, and

the word line driver is configured to apply one of the plurality of word line voltages to each word line associated to a same one of the plurality of groups.

3. The nonvolatile memory device of claim 1 , wherein the memory cell array includes a plurality of strings, and

each of the plurality of strings includes two or more of the plurality of memory cells connected between a string select transistor and a ground select transistor.

4. The nonvolatile memory device of claim 3 , wherein the word line driver is configured to apply the plurality of word line voltages to word lines of the two or more memory cells such that each of the word lines of the two or more memory cells receives one of the plurality of word line voltages with a magnitude based on a distance from the corresponding word line to a string select line connected to the string select transistor.

5. The nonvolatile memory device of claim 4 , wherein a greater the distance from the corresponding word line to the string select line, a lower the magnitude of the one of the plurality of word line voltages.

6. The nonvolatile memory device of claim 4 , wherein a greater the distance from the corresponding word line to the string select line, a greater the magnitude of the one of the plurality of word line voltages.

7. The nonvolatile memory device of claim 4 , wherein a greater a distance on a channel between the corresponding word line and the string select line in a first interval, a lower the magnitude of the one of the plurality of word line voltages, and

the greater the distance on the channel between the corresponding word line and the string select line in a second interval, a greater the magnitude of the one of the plurality of word line voltages.

8. The nonvolatile memory device of claim 3 , wherein at least two of the plurality of strings are connected to one bit line and share word lines.

9. The nonvolatile memory device of claim 1 , wherein the word line driver is configured to apply a program voltage to a selected word line during a program operation, a magnitude of the program voltage based on a location of the selected word line.

10. The nonvolatile memory device of claim 1 , wherein the word line driver is configured to apply a program voltage increment to a selected word line during a program operation, a magnitude of the program voltage increment based on a location of the selected word line.

11. The nonvolatile memory device of claim 1 , wherein the word line driver is configured to apply pass voltages to unselected word lines during a program operation, a magnitude of each of the pass voltages based on a location of each of the unselected word lines.

12. The nonvolatile memory device of claim 1 , wherein the word line driver is configured to apply unselect read voltages to unselected word lines during a read operation, a magnitude of each of the unselect read voltages based on a location of each of the unselected word lines.

13. The nonvolatile memory device of claim 1 , wherein the word line driver is configured to apply word line erase voltages to the plurality of word lines during an erase operation, a magnitude of each of the word line erase voltages based on a location of each of the plurality of word lines.

14. The nonvolatile memory device of claim 1 , wherein the plurality of memory cells are a plurality of memory cell groups, each memory cell group including each memory cell within a horizontal plane of the memory cell array.

15. A method for operating a nonvolatile memory device which includes a plurality of memory cells that are sequentially arranged in a vertical direction to a substrate, comprising:

determining a magnitude of a word line voltage of a word line based on a location of the word line; and

setting the word line voltage on the word line.

16. The method of claim 15 , wherein the determining of the magnitude of the word line voltage includes determining the magnitude of the word line voltage based on a distance between the word line and a string select line.

17. A memory system comprising a nonvolatile memory device which includes a plurality of memory cells that are sequentially arranged in a vertical direction to a substrate, comprising:

the nonvolatile memory device; and

a controller configured to control the nonvolatile memory device,

wherein the nonvolatile memory device includes

a memory cell array including the plurality of memory cells, and

a word line driver configured to apply a select voltage to a selected word line of a plurality of word lines connected to the plurality of memory cells, and to apply an unselect voltage to an unselected word line of the plurality of word lines, a magnitude of the select voltage determined according to a location of the selected word line.

18. The memory system claim 17 , wherein the nonvolatile memory device and the controller constitute a solid state drive (SSD).

19. The memory system claim 17 , wherein the nonvolatile memory device and the controller constitute a memory card.