Method for detecting and correcting errors for a memory whose structure shows dissymmetrical behavior, corresponding memory and its use
To produce a memory which resists ion or photon attack, a memory structure is chosen whose memory point behaves asymmetrically with regard to these attacks. It is shown that in this case, it is sufficient to have a reference cell for an identical and periodic storage structure in order to be able to correct all the memory cells assailed by an attack. An error correction efficiency of ½ is thus obtained, with a simple redundancy, whereas the conventional methods make provision, for the same result, to triple the storage, to obtain a less beneficial efficiency of ⅓.
1. Memory comprising:
memory cells, which are single or multiple cells, with dissymmetrical behavior wherein the dissymmetrical behavior is exhibited as a sensitivity of the memory cell in a first electrical state by which the memory cell changes from one of a first or a second electrical state to a corresponding one of a second or a first electrical state during an attack by irradiation, the sensitivity being lower for passing from the first state into the second state than for passing from the second state to the first state,
pairs of memory cells formed by the memory cells with dissymmetrical behavior,
wherein a first cell of a pair is charged with a first piece of binary information and a second cell of the pair is charged with a second piece of binary information,
a detector to detect that the first and second memory cells of a pair are charged with two pieces of contradictory information instead of two pieces of consistent information,
a reference memory cell associated with the pair of memory cells, the reference memory cell being loaded with a piece of information corresponding to the first state, and
a logic circuit to designate, as a function of the reference memory cell, that the cell of the memory cells of a pair that is in the second state has been affected by the irradiation when the states of the cells of the pair of cells are contradictory.
2. Memory according to claim 1 , wherein
the second piece of information corresponds to a same electrical state as that of the first piece of information so that these pieces of information are consistent,
contradictory pieces of information being then pieces of information corresponding to complementary electrical states.
3. Memory according claim 1 , wherein
the second piece of information corresponds to an electrical state complementary to that of the first piece of information so that these pieces of information are consistent,
contradictory pieces of information being then pieces of information corresponding to same electrical states.
4. Memory according to claim 1 , wherein
the detector detects that one of the cells of the pair which has changed its state owing to the irradiation, and the memory further includes
a logic circuit that designates the other cell as being the cell in a true state.
5. Memory according claim 1 , wherein
the pair reference memory cell is in the first state.
6. Memory according to claim 1 , wherein the pair of memory cells are of the DRAM or EPROM type.
7. Memory according to claim 1 , further comprising:
first and second bit rows connected to duplicated memory cells,
an exclusive- or gate connected to the first and second bit rows
a duplexer controlled by this exclusive- or gate,
the duplexer receiving, as inputs, one of the first and second bit rows and a bit row coming from the reference cell.
8. A personal computer including the memory according to claim 1 .
9. Method for detecting and correcting data errors stored in a memory, the memory cell of which has dissymmetrical behavior, comprising:
storing respective pieces of data to be corrected in two data banks,
detecting an error in one bank and
correcting the error with the content of the other bank, wherein
the memory cells in the two data banks exhibit a dissymmetrical behavior resulting from a sensitivity of one of the memory cells switching from one of first or second electrical state to a second or first electrical state, respectively, during an attack by irradiation, the sensitivity being lower for switching from the first state to the second state than for switching from the second state to the first state, the method further including:
arranging the memory cells in pairs,
loading a first cell of a pair with a first piece of binary information and a second cell of the pair with a second piece of binary information,
storing a piece of information corresponding to the first state in a reference memory cell associated with the pair of memory cells,
detecting that the memory cells of a pair are loaded with two pieces of contradictory information instead of two pieces of consistent information, and
designating, using a logic circuit, as a function of the pair and the reference memory cell, that one cell of the memory cells of the pair is in a true state.
10. Method according to claim 9 further including correcting the error after the error is detected.