Methods and apparatus for write-side intercell interference mitigation in flash memories

1. A method for writing to a flash memory device, comprising:

obtaining program data to be written to at least one target cell in said flash memory;

obtaining one or more bits of program data for at least one aggressor cell to be programmed later than said target cell; and

precompensating for intercell interference (ICI) for said target cell by generating precompensated program values, wherein a new program voltage of said at least one target cell that precompensates for said intercell interference is obtained by, subtracting an ICI cancelation term from an original program value of said at least one target cell.

2. The method of claim 1 , wherein said flash memory device is programmed using one or more of a page access technique and a wordline level access technique.

3. The method of claim 1 , wherein said at least one aggressor cell comprises one or more cells adjacent to said target cell.

4. The method of claim 3 , wherein said at least one aggressor cell comprises one or more adjacent cells in a same wordline as said target cell.

5. The method of claim 3 , wherein said at least one aggressor cell comprises one or more cells in an upper or lower adjacent wordline to said target cell.

6. The method of claim 3 , wherein at least one of said at least one aggressor cells is stored in a buffer until all of said at least one aggressor cells are available.

7. The method of claim 3 , wherein said at least one aggressor cell is identified by analyzing a programming sequence scheme employed for said flash memory device.

8. The method of claim 1 , wherein a new program voltage of said target cell that precompensates for said intercell interference is obtained with following equation:

PV tc (i,j) = PV t (i,j) −Δ V c   (2)

where PV t is the original program voltage; PV tc is the new program voltage after ICI cancellation and ΔV c is the ICI cancelation term.

9. The method of claim 8 , wherein said intercell interference mitigation term can be computed as follows:

Δ V c (i,j) =k x ΔV t (i,j−1) ( l )+ k x ΔV t (i,j+1) ( l )+ K y ΔV t (i+1,j) ( l ) + k xy ΔV t (i+1,j−1) ( l )+ k xy ΔV t (i+1,j+1) ( l )  (3)

where ΔV t (w,b) (l) is the change in the V t voltage of cell (w,b) when voltage level l is programmed into cell (w,b); lε{1,2, . . . L} is the voltage level; and k x ,k y ,and k xy are the capacitive coupling coefficients,

wherein different voltage levels 1 can be programmed into different target and aggressor cells.

10. The method of claim 1 , further comprising the step of providing said precompensated program values for said target cell on an interface for writing in a memory array of said flash memory device.

11. The method of claim 1 , wherein said obtaining steps obtain said program data to be written to at least one target cell and said one or more bits of program data for at least one aggressor cell from an interface and said precompensated program values are computed by a processor associated with said flash memory device.

12. The method of claim 1 , wherein said method is applied to one or more steps of a multi-step page programming sequence.

13. The method of claim 1 , wherein said step of determining intercell interference neglects intercell interference for said target cell from diagonally adjacent aggressor cells.

14. The method of claim 1 , wherein said step of determining intercell interference neglects intercell interference for said target cell from one or more adjacent cells in the same wordline for an even/odd programming sequence.

15. The method of claim 1 , further comprising the step of providing said precompensated program values for said target cell to the flash memory.

16. The method of claim 1 , wherein voltage shift properties of a multi-step programming sequence are employed to reduce a number of distinct voltage shifts ΔV c values to be computed to M k , wherein M<L, k is a number of considered aggressor cells and M is the number of distinct voltage shifts that are considered,

17. A system for writing to a flash memory device, comprising:

a memory; and

at least one processor, coupled to the memory, operative to:

obtain program data to be written to at least one target cell in said flash memory;

obtain one or more bits of program data for at least one aggressor cell to be programmed later than said target cell; and

precompensate for intercell interference for said target cell by generating precompensated program values, wherein a new program voltage of said at least one target cell that precompensates for said intercell interference is obtained by subtracting an ICI cancelation term from an original pro am value of said at least one target cell.

18. The method of claim 11 , wherein during a write operation said interface transfers program data to be stored in said target cell and said at least one aggressor cell and said precompensated program values are computed inside said flash memory device.

19. The method of claim 11 , wherein said interface conveys values representing information associated with said at least one aggressor cell.

20. The method of claim 11 , wherein said interface employs Double Data Rate (DDR) techniques.

21. The method of claim 1 , wherein said precompensating step is performed by a flash control system that is connected to said flash memory device by an interface that transfers said precompensated program values to be stored in said at least one target cell.

22. The method of claim 21 , wherein said precompensated program values are transferred by said flash control system during a write operation.

23. The method of claim 1 , wherein said precompensated program values are represented using a greater number of bits than said original program value.

24. The method of claim 1 , wherein said precompensated program values are computed outside of said flash memory device.