Methods and apparatus for interfacing between a flash memory controller and a flash memory array
View Patent ↗Methods and apparatus are provided for interfacing between a flash memory controller and a flash memory array. The interface comprises a communication channel between the flash memory controller and the flash memory array, wherein the communication channel carries data for a target cell in the flash memory array on a first edge of a clock signal and wherein the communication channel carries additional information for the target cell on a second edge of the clock signal. For an exemplary write access, the additional information comprises, for example, information about one or more aggressor cells associated with the target cell. For an exemplary read access, the additional information comprises, for example, soft information for the data for the target cell transmitted on the first edge.
1. A method for interfacing between a flash memory controller and a flash memory array, comprising:
transmitting data for a target cell in said flash memory array using a first edge of a clock signal; and
transmitting additional information for said target cell using a second edge of said clock signal, wherein a type of each edge of said clock signal is one of a falling edge type and a rising edge type, wherein said type of said first edge of said clock signal is different than said type of said second edge of said clock signal, and wherein said transmitted additional information comprises a different type of information than said transmitted data.
2. The method of claim 1 , wherein said transmitting steps comprise a write access and wherein said transmitted additional information comprises information about one or more aggressor cells associated with said target cell.
3. The method of claim 2 , wherein said information about said one or more aggressor cells comprises one or more bits of program data for said one or more aggressor cells.
4. The method of claim 1 , wherein said transmitting steps comprise a read access and wherein said transmitted additional information comprises soft information for said data for said target cell transmitted on said first edge.
5. The method of claim 1 , wherein said first edge comprises a rising edge and said second edge comprises a falling edge.
6. A method for interfacing between a flash memory controller and a flash memory array, comprising:
receiving data for a target cell in said flash memory array on a first edge of a clock signal; and
receiving additional information for said target cell on a second edge of said clock signal, wherein a type of each edge of said clock signal is one of a falling edge type and a rising edge type, wherein said type of said first edge of said clock signal is different than said type of said second edge of said clock signal, and wherein said received additional information comprises a different type of information than said received data.
7. The method of claim 6 , wherein said receiving steps comprise a write access and wherein said received additional information comprises information about one or more aggressor cells associated with said target cell.
8. The method of claim 7 , wherein said information about said one or more aggressor cells comprises one or more bits of program data for said one or more aggressor cells.
9. The method of claim 6 , wherein said receiving steps comprise a read access and wherein said received additional information comprises soft information for said data for said target cell transmitted on said first edge.
10. The method of claim 6 , wherein said first edge comprises a rising edge and said second edge comprises a falling edge.
11. An interface for interfacing between a flash memory controller and a flash memory array, comprising:
a communication channel between said flash memory controller and said flash memory array, wherein said communication channel carries data for a target cell in said flash memory array on a first edge of a clock signal and wherein said communication channel carries additional information for said target cell on a second edge of said clock signal, wherein a type of each edge of said clock signal is one of a failing edge type and a rising edge type, wherein said type of said first edge of said clock signal is different than said type of said second edge of said clock signal, and wherein said additional information comprises a different type of information than said data.
12. The interface of claim 11 , wherein for a write access, said additional information comprises information about one or more aggressor cells associated with said target cell.
13. The interface of claim 12 , wherein said information about said one or more aggressor cells comprises one or more bits of program data for said one or more aggressor cells.
14. The interface of claim 11 , wherein for a read access, said additional information comprises soft information for said data for said target cell transmitted on said first edge.
15. The interface of claim 11 , wherein said first edge comprises a rising edge and said second edge comprises a falling edge.