IP Library Granted Patent US 8,788,923
Granted Patent B2
US 8,788,923 · App. 13/001,317 · Granted Jul 22, 2014

Methods and apparatus for soft demapping and intercell interference mitigation in flash memories

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Quick Facts
Patent No.
US 8,788,923
App. No.
13/001,317
Granted
Jul 22, 2014
Kind
B2
Abstract

Methods and apparatus are provided for soft demapping and intercell interference mitigation in flash memories. In one variation, a target cell in a flash memory device capable of storing at least two data levels, s, per cell is read by obtaining a measured read value, r, for at least one target cell in the flash memory; obtaining a value, h, representing data stored for at least one aggressor cell in the flash memory; selecting one or more probability density functions based on a pattern of values stored in at least a portion of the flash memory, wherein the probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on the at least one target cell in the flash memory; evaluating at least one selected probability density function based on the measured read value, r; and computing one or more log likelihood ratios based on a result of the evaluating step.

Claims (397)

1. A method for reading a target cell in a flash memory device capable of storing at least two data levels, s, per cell, said method comprising:

obtaining a measured read value, r, for at least one target cell in said flash memory;

evaluating at least one probability density function based on said measured read value, r, wherein said probability density function indicates a probability of measuring a read value, r, for a given data level, s; and

computing one or more log likelihood ratios based on a result of said evaluating step; wherein said computing step further comprises the step of:

aggregating for each of two possible binary values said probability of measuring a read value, r, for a given data level, s, for multiple data levels associated with said two possible binary values.

2. The method of claim 1 , wherein said probability density function further comprises an expression of disturbance on said target cell.

3. The method of claim 1 , wherein said probability density function further comprises an expression of pattern-dependent disturbance of one or more aggressor cells on at least one target cell in said flash memory.

4. The method of claim 1 , further comprising the step of forming a ratio based on said aggregated probabilities for each of said two possible binary values.

5. The method of claim 1 , further comprising the step of multiplying said aggregated probabilities for each of said two possible binary values by an expression based on one or more a priori probability values for all bits within a cell other than a bit for which said log likelihood ratio is being computed.

6. The method of claim 1 , where said aggregating comprises one or more of a sum and a multiplication.

7. The method of claim 1 , wherein said computing step evaluates the following expression:

L

e

(

C

t

)

=

log

s

χ

0

t

p

(

r

s

)

·

q

=

1

,

q

t

m

exp

(

-

L

a

(

C

q

)

·

c

q

)

s

χ

1

t

p

(

r

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)

·

r

=

1

,

q

t

m

exp

(

-

L

a

(

C

q

)

·

c

q

)

(

2

)

where p(r|s) are the probability density functions characterizing the flash memory; c q is the coded bit, m is the number of bits per cell, L a (C t ) is the log likelihood ratio, L a (C q ) is the log likelihood ratio for encoded bit C q , L e (C t ) is extrinsic log likelihood ratio, and χ c ti t is a subset of symbols whose bit labels have the value C t =c t on position t.

8. The method of claim 1 , wherein said disturbance comprises one or more of back pattern dependency, intercell interference, program disturb, read disturb and additional noise.

9. The method of claim 1 , wherein said probability density function is represented as one or more of a stored table and an expression.

10. A method for reading a target cell in a flash memory device capable of storing at least two data levels, s, per cell, said method comprising:

obtaining a measured read value, r, for at least one target cell in said flash memory;

obtaining a value, h, representing data stored for at least one aggressor cell in said flash memory;

selecting one or more probability density functions based on a pattern of values stored in at least a portion of said flash memory, wherein said probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on said at least one target cell in said flash memory;

evaluating at least one selected probability density function based on said measured read value, r; and

computing one or more log likelihood ratios based on a result of said evaluating step.

11. The method of claim 10 , wherein said value, h, is one or more of a hard decision and a soft value.

12. The method of claim 10 , wherein said computing step further comprises the step of aggregating for each of two possible binary values said probability of measuring a read value, r, for a given data level, s, for all data levels associated with said two possible binary values.

13. The method of claim 12 , further comprising the step of forming a ratio based on said aggregated probabilities for each of said two possible binary values.

14. The method of claim 12 , further comprising the step of multiplying said aggregated probabilities for each of said two possible binary values by an expression based on one or more a priori probability values for all bits within a cell other than a bit for which said log likelihood ratio is being computed.

15. The method of claim 12 , where said aggregating comprises one or more of a sum and a multiplication.

16. The method of claim 12 , wherein said evaluating step determines a pattern-dependent probability of measuring a read value, r, for a given data level, s, for a given pattern of values stored in said one or more aggressor cells.

17. The method of claim 10 , wherein said computing step evaluates the following expression:

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e

(

C

t

)

=

log

s

χ

0

t

p

(

r

s

,

h

(

i

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,

h

(

i

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1

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,

h

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i

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)

)

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m

exp

(

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c

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χ

1

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(

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h

(

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h

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h

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q

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m

exp

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c

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(

3

)

where h (i,j) are voltage levels of the aggressor cells, based on the hard output of said flash memory, p(r|s) are the probability density functions characterizing the flash memory; r is the received signal, s is the noiseless signal, c q is the coded bit, m is the number of bits per cell, L a (C t ) is the log likelihood ratio, L a (C q ) is the log likelihood ratio for encoded bit C q , L e (C t ) is extrinsic log likelihood ratio, and χ c ti t is a subset of symbols whose bit labels have the value C t =c t on position t.

18. The method of claim 10 , wherein said probability density functions further comprise one or more of back pattern dependency, intercell interference, program disturb, read disturb and additional noise.

19. The method of claim 10 , wherein said probability density function is represented as one or more of a stored table and an expression.

20. The method of claim 10 , further comprising the step of performing multiple iterations using soft information.

21. The method of claim 10 , wherein at least one of said one or more probability density functions comprises a histogram.

22. The method of claim 10 , wherein at least one of said one or more probability density functions is expressed using a Gaussian approximation.

23. The method of claim 10 , wherein at least one of said one or more probability density functions is based on a trellis-based algorithm.

24. A method for characterizing disturbance in a flash memory, comprising:

obtaining one or more probability density functions that express pattern-dependent disturbance of one or more aggressor cells on at least one target cell; and

selecting one or more of said probability density functions based on a pattern of values stored in at least a portion of said flash memory.

25. The method of claim 24 , wherein said disturbance comprises one or more of back pattern dependency, intercell interference, program disturb, read disturb and additional noise.

26. The method of claim 24 , wherein said probability density function is represented as one or more of a stored table and an expression.

27. The method of claim 24 , further comprising the step of updating said probability density function based on one or more data decisions.

28. A system for reading a target cell in a flash memory device capable of storing at least two data levels, s, per cell, comprising:

a memory; and

at least one processor, coupled to the memory, operative to:

obtain a measured read value, r, for at least one target cell in said flash memory;

evaluate at least one probability density function based on said measured read value, r, wherein said probability density function indicates a probability of measuring a read value, r, for a given data level, s; and

compute one or more log likelihood ratios based on a result of said evaluation; wherein said computation comprises aggregating for each of two possible binary values said probability of measuring a read value, r, for a given data level, s, for multiple data levels associated with said two possible binary values.

29. The system of claim 28 , wherein said at least one hardware device is further configured to form a ratio based on said aggregated probabilities for each of said two possible binary values.

30. The system of claim 28 , wherein said at least one hardware device is further configured to multiply said aggregated probabilities for each of said two possible binary values by an expression based on one or more a priori probability values for all bits within a cell other than a bit for which said log likelihood ratio is being computed.

31. The system of claim 28 , wherein said aggregating comprises one or more of a sum and a multiplication.

32. The system of claim 28 , wherein said computation of one or more log likelihood ratios evaluates the following expression:

L

e

(

C

t

)

=

log

s

χ

0

t

p

(

r

s

)

·

q

=

1

,

q

t

m

exp

(

-

L

a

(

C

q

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·

c

q

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s

χ

1

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p

(

r

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r

=

1

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q

t

m

exp

(

-

L

a

(

C

q

)

·

c

q

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(

2

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where p(r|s) are the probability density functions characterizing the flash memory; c q is the coded bit, m is the number of bits per cell, L a (C t ) is the log likelihood ratio, L a (C q ) is the log likelihood ratio for encoded bit C q , L e (C t ) is extrinsic log likelihood ratio, and

χ c t1 t is a subset of symbols whose bit labels have the value C i =c t on position t.

33. A system for reading a target cell in a flash memory device capable of storing at least two data levels, s, per cell, comprising:

a memory; and

at least one processor, coupled to the memory, operative to:

obtain a measured read value, r, for at least one target cell in said flash memory;

obtain a value, h, representing data stored for at least one aggressor cell in said flash memory;

select one or more probability density functions based on a pattern of values stored in at least a portion of said flash memory, wherein said probability density functions comprises pattern-dependent disturbance of one or more aggressor cells on said at least one target cell in said flash memory;

evaluate at least one selected probability density function based on said measured read value, r; and

compute one or more log likelihood ratios based on a result of said evaluation.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: HAY, HENRY M., MR.; WEBER, BRUCE A., MR.
To: HAWKES DESIGN AND CONSULTING, LLC
Reel/Frame 041143/0345 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 8, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 037234/0034 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Mar 19, 2015
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 035226/0230 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 22, 2011
From: HARATSCH, ERICH F.; IVKOVIC, MILOS; KRACHKOVSKY, VICTOR; MILADINOVIC, NENAD; VITYAEV, ANDREI; YEN, JOHNSON
To: LSI CORPORATION
Reel/Frame 026475/0514 →