Memory cell array, nonvolatile storage device, memory cell, and method of manufacturing memory cell array
View Patent ↗A method of manufacturing a memory cell array in which first conductive layers ( 2 ) and second conductive layers ( 14 ) extend above a semiconductor substrate ( 1 ) and three-dimensionally cross with each other, and memory cells each of which includes a current steering element ( 10 ) and a variable resistance element ( 23 ) electrically connected in series to each other is provided at a corresponding one of three-dimensional cross points between the first conductive layers ( 2 ) and the second conductive layers ( 14 ). The method includes: forming a first interlayer insulating film ( 3 ); forming a contact hole in the interlayer insulating film ( 3 ); depositing a first plug material ( 4 ) in the contact hole and on the first interlayer insulating film ( 3 ); performing a first polishing in which the first plug material ( 4 ) is polished until the first interlayer insulating film ( 3 ) is exposed; depositing a conductive film ( 6 a ) that becomes a first electrode ( 6 ) of the current steering element ( 10 ), on the first plug material ( 4 ) and the first interlayer insulating film ( 3 ) after the first polishing; and performing a second polishing in which a surface of the conductive film ( 6 a ) is polished.
1. A memory cell array comprising:
a semiconductor substrate;
first conductive layers arranged to extend in parallel to each other on said semiconductor substrate;
an interlayer insulating film formed to cover said first conductive layers;
second conductive layers arranged above said interlayer insulating film to extend in parallel to each other and to three-dimensionally cross with said first conductive layers;
plugs each formed to penetrate through said interlayer insulating film and to have a lower surface electrically connected to a corresponding one of said first conductive layers at a corresponding one of three-dimensional cross points between said first conductive layers and said second conductive layers; and
memory cells each formed between, and electrically connected to, an upper surface of a corresponding one of said plugs and a corresponding one of said second conductive layers, at the corresponding one of three-dimensional cross points between said first conductive layers and said second conductive layers,
wherein each of said memory cells includes:
a current steering element formed to cover said upper surface of the corresponding one of said plugs, said current steering element having a nonlinear current-voltage characteristic, and
a variable resistance element which is electrically connected in series to said current steering element and has a resistance value that reversibly changes in response to an application of a voltage pulse,
said upper surface of each of said plugs is formed to have a first concave shape,
said current steering element includes: a first electrode that covers said upper surface of the corresponding one of said plugs; a current steering layer formed on said first electrode; and a second electrode formed on said current steering layer, and
said first electrode is thicker above a center portion than above a peripheral portion of said upper surface of the corresponding one of said plugs, by a maximum of a depth of the first concave shape.
2. The memory cell array according to claim 1 ,
wherein said first electrode has an upper surface having a second concave shape above said upper surface of the corresponding one of said plugs, the second concave shape having a depth smaller than a thickness of said current steering layer.
3. The memory cell array according to claim 1 ,
wherein said first electrode has an upper surface formed substantially flat above said upper surface of the corresponding one of said plugs.
4. The memory cell array according to claim 1 ,
wherein said variable resistance element includes: a variable resistance layer formed in contact with said second electrode of said current steering element; and a third electrode formed on said variable resistance layer,
said second electrode, said variable resistance layer, and said third electrode forming a stacked structure of said variable resistance element.
5. The memory cell array according to claim 1 ,
wherein said first electrode or said second electrode includes tantalum nitride and said current steering layer includes silicon nitride.
6. A nonvolatile storage device comprising:
the memory cell array according to claim 1 ; and
a decoder for driving the memory cell array.
7. A memory cell formed on a plug that includes a concave surface exposed to a surface of an interlayer insulating film, said memory cell comprising:
a current steering element formed to cover the surface of the plug and having a nonlinear current-voltage characteristic; and
a variable resistance element which is electrically connected in series to said current steering element and has a resistance value that reversibly changes in response to an application of a voltage pulse,
wherein said current steering element includes: a first electrode that covers the surface of the plug; a current steering layer formed on said first electrode; and a second electrode formed on said current steering layer, and
said first electrode is thicker above a center portion than above a peripheral portion of the surface of the plug, by a maximum of a depth of the first concave shape of the surface of the plug.