IP Library Granted Patent US 8,680,458
Granted Patent B2
US 8,680,458 · App. 13/002,043 · Granted Mar 25, 2014

Data transmission through optical vias

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Quick Facts
Patent No.
US 8,680,458
App. No.
13/002,043
Granted
Mar 25, 2014
Kind
B2
Abstract

Technologies generally described herein relate to multilayer circuit boards with optical vias for data transmission between the layers. One or more regions may be created on a multilayer circuit board for optical vias. A transparent conducting oxide (TCO) layer can be deposited on a top and/or bottom layer of the circuit board. P-N junctions can be created over the TCO layer about the one or more regions to form optical vias as photo-emitting and/or photo-detecting components. The photo-emitting and/or photo-detecting components may be coupled to electronic components on the multilayer circuit board.

Claims (47)

1. A multilayer circuit board with optical vias for data transmission between two or more layers, the circuit board comprising:

a circuit board with two or more conductive layers separated by a dielectric layer;

an optical via configured to provide an optical transmission path between the two or more conductive layers of the circuit board;

a transparent conductive oxide layer deposited on a top layer of the circuit board, wherein the transparent conductive oxide layer is implanted with n-type impurities and patterned to form light emitting diodes (LEDs) about a region for the optical via to create a p-n junction;

an LED coupled to one end of the optical via and configured to convert incident electrical signals to optical signals; and

a photo-detector component coupled to another end of the optical via and configured to convert the optical signals to received electrical signals.

2. The multilayer circuit board according to claim 1 , wherein the transparent conductive oxide layer comprises one of SnO 2 , ZnO, and indium tin oxide (ITO).

3. The multilayer circuit board according to claim 1 , wherein the photo-detector component comprises one or more of a p-n junction photodiode, a p-i-n photodiode, an avalanche photodiode, and/or a metal-semiconductor-metal (MSM) photo-detector.

4. The multilayer circuit board according to claim 1 , further comprising an electrical component electrically coupled to the LED and another electrical component electrically coupled to the photo-detector component.

5. The multilayer circuit board according to claim 1 , wherein the optical via corresponds to one member of an array of optical vias associated with the multilayer circuit board.

6. The multilayer circuit board according to 5 , wherein the circuit board includes a plurality of conductive layers and at least one of the optical vias is configured to provide data transmission between a top conductive layer of the plurality of conductive layers and an inner conductive layer of the plurality of conductive layers.

7. A method to manufacture a multilayer circuit board with optical vias for data transmission between two or more layers of the multilayer circuit board, the method comprising:

creating one or more regions of the multilayer circuit board for optical vias;

depositing a transparent conductive oxide (TCO) layer on a top layer of the multilayer circuit board;

creating p-n junctions about the one or more regions for the optical vias by implanting the TCO layer with n-type impurities and patterning the TCO layer to form light emitting diodes (LEDs) about the regions for the optical vias; and

creating electrical connections to the p-n junctions acting as the LEDs.

8. The method according to claim 7 , further comprising:

depositing a transparent conducting oxide (TCO) layer on a bottom layer of the multilayer circuit board;

creating p-n junctions, in the TCO layer deposited on the bottom layer and about the one or more regions, to act as photodiodes for the optical vias; and

creating electrical couplings to the p-n junctions acting as photodiodes.

9. The method according to claim 7 , wherein creating the electrical connections to the p-n junctions comprises:

depositing a dielectric layer over the patterned TCO layer while leaving the one or more regions of the multilayer circuit board for electrical vias over the p-n junctions;

planarizing the dielectric layer; and

filling the electrical vias with a metallic material to provide electrical connections to the LEDs.

10. The method according to claim 7 , further comprising:

placing electrical components on one or more of the top layer and/or a bottom layer of the multilayer circuit board.

11. The method according to claim 7 , further comprising:

forming a p-n junction in an inner layer of the multilayer circuit board, wherein an optical via is configured to couple a top layer of the multilayer circuit board and the inner layer of the multilayer circuit board.

12. An apparatus to control manufacture of a multilayer circuit board with optical vias for data transmission between two or more layers of the multilayer circuit board, the apparatus comprising:

a memory with instructions stored thereon; and

a processor coupled to the memory and configured to execute the instructions, which in response to execution by the processor, cause the apparatus to:

create one or more regions for optical vias in the multilayer circuit board for data transmission between electrical components located on top and bottom layers of the multilayer circuit board;

deposit a transparent conductive oxide (TCO) layer on the top and bottom layers of the multilayer circuit board;

create p-n junctions about the one or more regions for the optical vias at the top and bottom layers by implantation of the TCO layer with n-type impurities; and

create electrical couplings to the p-n junctions, wherein the p-n junctions are effective to act as either light emitting diodes (LEDs) or photodiodes.

13. The apparatus according to claim 12 , wherein to create the electrical couplings to the p-n junctions, the instructions are executable by the processor to cause the apparatus to:

deposit a dielectric layer over the TCO layer;

planarize the dielectric layer;

create the one or more regions for electrical vias over the p-n junctions; and

fill the electrical vias with a metallic material to provide electrical couplings to the LEDs.

14. The apparatus according to claim 13 , wherein the instructions are further executable by the processor to cause the apparatus to:

place electrical components on the top and bottom layers of the multilayer circuit board; and

couple at least some of the electrical components to the p-n junctions that act as LEDs and photodiodes.

15. The apparatus according to claim 13 , wherein the dielectric layer comprises tetraethyl orthosilicate (TEOS).

16. The apparatus according to claim 13 , wherein the metallic material comprises tungsten.

17. The apparatus according to claim 13 , wherein the electrical vias and the optical vias are formed in respective regions for the electrical vias and optical vias by one or more of etching and/or drilling.

18. The apparatus according to claim 12 , wherein the transparent conductive oxide layer comprises one of SnO 2 , ZnO, and indium tin oxide (ITO).

Assignments (5)
RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED ON JANUARY 29, 2019 AT REEL 048373 FRAME 0217 Recorded Sep 22, 2025
From: CRESTLINE DIRECT FINANCE, L.P., AS COLLATERAL AGENT
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 072936/0464 →
SECURITY INTEREST Recorded Jan 29, 2019
From: EMPIRE TECHNOLOGY DEVELOPMENT LLC
To: CRESTLINE DIRECT FINANCE, L.P.
Reel/Frame 048373/0217 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2011
From: SIEVERS, MICHAEL RAY
To: H&C SCIENTIFIC RESOURCES INTERNATIONAL, LLC
Reel/Frame 025703/0754 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2011
From: H&C SCIENTIFIC RESOURCES INTERNATIONAL, LLC
To: EMPIRE TECHNOLOGY DEVELOPMENT, LLC
Reel/Frame 025703/0803 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 10, 2011
From: SIEVERS, MICHAEL RAY
To: H&C SCIENTIFIC RESOURCES INTERNATIONAL
Reel/Frame 025611/0432 →