Nonaligned access to random access memory
View Patent ↗Memory apparatus including a byte-bank organized in N rows and 8 columns, having a capacity of log 2 (N) bytes, a log 2 (N) bit address bus operative to address the byte-bank, an address offset bus operative to generate offsets (e.g., one-bit offsets) to bits of the byte-bank with an address conversion operator, and an adder in operative communication with the address offset bus and the log 2 (N) bit address bus, the adder operative to add addresses of the byte-bank with the offset generated by the address conversion operator and output a result to the log 2 (N) bit address. A random access memory array may include a plurality of the byte-banks.
1. Memory apparatus comprising:
a byte-bank organized in N rows and 8 columns, having a capacity of log 2 (N) bytes;
a log 2 (N) bit address bus operative to address said byte-bank;
an address offset bus operative to generate address offsets to bits of said byte-bank with an address conversion operator; and
an adder in operative communication with said address offset bus and said log 2 (N) bit address bus, said adder operative to add addresses of said byte-bank with the address offset generated by said address conversion operator and output a result to said log 2 (N) bit address.
2. The memory apparatus according to claim 1 , wherein said address offsets comprise one-bit address offsets.
3. The memory apparatus according to claim 1 , further comprising a random access memory array comprising a plurality of said byte-banks.
4. The memory apparatus according to claim 3 , wherein for each byte-bank, said address conversion operator is operative to convert an unaligned address on a byte resolution into a log 2 (N) address on a data word resolution.
5. The memory apparatus according to claim 4 , wherein said address offsets comprise one-bit address offsets.
6. The memory apparatus according to claim 1 , wherein said address offset comprises shifting the most significant byte from the least significant byte by a distance of 8 bytes.
7. A method comprising:
providing a random access memory array comprising a plurality of said byte-banks, wherein each byte-bank is organized in N rows and 8 columns, each byte-bank having a capacity of log 2 (N) bytes;
providing a log 2 (N) bit address bus operative to address said byte-bank;
generating address offsets to bits of said byte-bank with an address conversion operator; and
adding addresses of said byte-bank with the generated address offset and outputting a result to said log 2 (N) bit address.
8. The method according to claim 7 , wherein generating the address offsets comprises generating one-bit address offsets.
9. The method according to claim 7 , further comprising, for each byte-bank, converting an unaligned address on a byte resolution into a log 2 (N) address on a data word resolution.
10. The method according to claim 7 , wherein generating the address offsets comprises shifting the most significant byte from the least significant byte by a distance of 8 bytes.
11. The method according to claim 7 , further comprising performing an unaligned memory access to said byte-banks.
12. The method according to claim 11 , wherein the unaligned memory access comprises transforming a data word before a memory write operation and compensating for the data word rotation with the address offsets.
13. The method according to claim 11 , wherein the unaligned memory access comprises transforming a data word before a memory read operation and compensating for the data word rotation with the address offsets.
14. An apparatus comprising:
a memory array comprising a plurality of byte banks, wherein individual ones of the plurality of byte banks have a capacity of a number of bytes; and
a plurality of row decoders, individual of the plurality of row decoders capable of being selectively coupled with the memory array, wherein individual ones of the row decoders are coupled to respective individual ones of the plurality of byte banks;
wherein when selectively coupled to the memory array the plurality of row decoders may be capable of providing nonaligned access to the memory array;
an address bus coupled to the plurality of byte banks, wherein the address bus has a width of a number of bits equal to the number of bytes, and wherein the address bus is configured to address the respective individual ones of the byte banks using the number of bits; and
a plurality of address offset buses, individual ones of the plurality of address offset buses associated with respective individual ones of the plurality of byte banks.
15. The apparatus of claim 14, wherein the memory array comprises an SRAM memory array.
16. The apparatus of claim 14, wherein individual ones of the plurality of address offset buses are 1-bit buses.
17. The apparatus of claim 14, further comprising:
a plurality of adders, wherein individual ones of the plurality of adders are configured to receive a word address and a respective input from one of the plurality of address offset buses, wherein individual ones of the plurality of adders are configured to add the word address and the input received from one of the plurality of address offset buses, and wherein individual ones of the plurality of adders are configured to output an address to the address bus.
18. The apparatus of claim 14, further comprising:
an address conversion operator coupled to the plurality of address offset buses and configured to generate address offsets.