Semiconductor device
This invention provides a multi-pin semiconductor device as a low-cost flip-chip BGA. In the flip-chip BGA, a plurality of signal bonding electrodes in a peripheral area of the upper surface of a multilayer wiring substrate are separated into inner and outer ones and a plurality of signal through holes coupled to a plurality of signal wirings drawn inside are located between a plurality of rows of signal bonding electrodes and a central region where a plurality of bonding electrodes for core power supply are located so that the chip pad pitch can be decreased and the cost of the BGA can be reduced without an increase in the number of layers in the multilayer wiring substrate.
1. A semiconductor device comprising:
a multilayer wiring substrate having a first layer and a second layer, bonding electrodes arranged over a first main surface of the first layer, external terminals arranged over a second main surface of the second layer which faces a direction opposite a direction which the first main surface faces; and
a semiconductor chip having an obverse surface over which electrode pads are arranged and a reverse surface opposite the obverse surface, the semiconductor chip being mounted over the first main surface of the multilayer wiring substrate such that the obverse surface of the semiconductor chip faces the first main surface of the multilayer wiring substrate, each of the electrode pads of the semiconductor chip is electrically connected to each of the bonding electrodes of the multilayer wiring substrate via a conductive material,
wherein, in plan view, first bonding electrodes and second bonding electrodes located inside the first bonding electrodes among the bonding electrodes are arranged in a first region of the first main surface of the multilayer wiring substrate,
wherein, in plan view, third bonding electrodes among the bonding electrodes are arranged in a second region located inside the first region,
wherein all of the first bonding electrodes are signal bonding electrodes,
wherein the second bonding electrodes include signal bonding electrodes, first power supply bonding electrodes, and first ground (GND) bonding electrodes,
wherein the third bonding electrodes include second power supply bonding electrodes and second ground (GND) bonding electrodes,
wherein, in plan view, each of first wirings drawn from each of the first bonding electrodes extends toward an outside of the multilayer wiring substrate,
wherein, in plan view, each of second wirings drawn from each of the second bonding electrodes extends toward an inside of the multilayer wiring substrate,
wherein each of the second wirings drawn from the signal bonding electrodes among the second bonding electrodes is electrically connected to a first wiring portion in a different layer from the first layer via a first through hole,
wherein each of the second wirings drawn from the first power supply bonding electrodes among the second bonding electrodes is electrically connected to a second wiring portion in the different layer from the first layer via a second through hole,
wherein each of the second wirings drawn from the first ground (GND) bonding electrodes among the second bonding electrodes is electrically connected to a third wiring portion in the different layer from the first layer via a third through hole, and
wherein, in plan view, the first through hole is located between the first and the second regions and the first through hole is located inside the second and third through holes.
2. The semiconductor device according to claim 1 ,
wherein the first power supply bonding electrodes are Input/Output (IO) power supply bonding electrodes and the second power supply bonding electrodes are core power supply bonding electrodes.
3. The semiconductor device according to claim 1 ,
wherein, in the plan view, a part of the second wirings electrically connected to the first through holes is located between the second and third through holes.
4. The semiconductor device according to claim 1 ,
wherein each of the first and second bonding electrodes is arranged along a first direction, and
wherein, in a second direction perpendicular to the first direction, each of the first and second bonding electrodes is arranged in a same position.
5. The semiconductor device according to claim 1 ,
wherein the multilayer wiring substrate has a third layer between the first and second layer in a thickness direction of the multilayer wiring substrate,
wherein a first ground (GND) plane is formed between the first and third layers, and
wherein the third through hole is electrically connected to the first ground (GND) plane.
6. The semiconductor device according to claim 5 ,
wherein a first power supply plane is formed between the second and third layers, and
wherein the second through hole is electrically connected to a first power supply plane.
7. The semiconductor device according to claim 5 ,
wherein the first wiring portion is formed between the second and third layers.
8. The semiconductor device according to claim 5 ,
wherein a second ground (GND) plane is formed between the first and third layers, and
wherein each of the second ground (GND) bonding electrodes among the third bonding electrodes is electrically connected to the second ground (GND) plane via each of fourth through holes.
9. The semiconductor device according to claim 8 ,
wherein a second power supply plane is formed between the second and third layers, and
wherein each of the second power supply bonding electrodes among the third bonding electrodes is electrically connected to the second power supply plane via each of fifth through holes.
10. The semiconductor device according to claim 1 ,
wherein the multilayer wiring substrate has a core layer between the first and second layer in a thickness direction of the multilayer wiring substrate.
11. The semiconductor device according to claim 1 ,
wherein the conductive material includes solder.
12. The semiconductor device according to claim 1 ,
wherein the semiconductor chip has first electrode pads and second electrode pads arranged along an outer edge of the semiconductor chip, and
wherein each of the first and second electrode pads corresponds with each of the first and second bonding electrodes of the multilayer wiring substrate.
13. The semiconductor device according to claim 1 ,
wherein a resin is filled between the obverse surface of the semiconductor chip and the first main surface of the multilayer wiring substrate.
14. The semiconductor device according to claim 1 ,
wherein solder balls are electrically connected to each of the external terminals of the multilayer wiring substrate.