DRAM refresh schedule control module

1. An electronic device comprising a memory control circuit that controls a DRAM,

wherein the memory control circuit performs:

a first distributed refresh process for issuing refresh commands to the DRAM at a predetermined interval so that storage elements of which the DRAM is configured are refreshed at least once in a predetermined period Ts;

a concentrated refresh process for issuing, triggered by a predetermined request which is different from refresh commands to the DRAM, a predetermined number of times Nc of burst refresh commands in a burst having been issued in the concentrated refresh process at an interval in the predetermined period Ts that is shorter than the predetermined interval; and

a second distributed refresh process for, when the predetermined number of times Nc of refresh commands have been issued and a concentrated refresh process has been performed in the predetermined period Ts, calculating a refresh interval Tr for refreshing remaining storage elements to the DRAM that have not yet been refreshed in the predetermined period Ts and issues refresh commands at the calculated refresh interval Tr.

2. The electronic device according to claim 1 ,

wherein in the second distributed refresh process, the refresh interval Tr is calculated using Nr=Ns−Nb−Nc and Tr=(Ts−Tb−Tc)/Nr,

where Ns is the total predetermined number of times it is necessary to issue a refresh command in order to refresh the storage elements of which the DRAM is configured at least once within the predetermined period Ts, Nb is the number of times a refresh command is issued in the first distributed refresh process, Nc is the number of times a refresh command is issued in the concentrated refresh process, Nr is the number of times it is necessary to issue a refresh command in order to refresh the remaining storage elements that have not yet been refreshed in the predetermined period Ts, Tb is the time required to issue refresh commands in the first distributed refresh process, and Tc is the time required to issue refresh commands in the concentrated refresh process.

3. The electronic device according to claim 1 ,

wherein the memory control circuit changes the set values regarding the issuance o refresh commands in the first distributed refresh process, the concentrated refresh process, and the second distributed refresh process each time the predetermined period Ts passes.

4. The electronic device according to claim 1 , wherein in the concentrated refresh process, the number of times Nc that a refresh command is issued is changed based on the type of request to the DRAM.

5. The electronic device according to claim 1 , wherein in the concentrated refresh process, the same predetermined number Nc of refresh commands is issued, triggered by multiple types of requests to the DRAM.

6. The electronic device according to claim 1 ,

wherein the electronic device is an image reading apparatus; and

in the concentrated refresh process, the refresh commands are issued in a burst, triggered by an image read request.

7. The electronic device according to claim 1 ,

wherein the electronic device is a printing apparatus; and

in the concentrated refresh process, the refresh commands are issued in a burst, triggered by at least one of a color correction request and a screen process request.

8. The electronic device according to claim 1 ,

wherein the memory control circuit:

issues refresh commands consistently at the predetermined interval during the predetermined period Ts in the case where a first mode has been set;

issues the total number of times Ns that refresh commands are to be issued in a burst at a predetermined timing within the predetermined period Ts, in the case where a second mode has been set; and

performs the first distributed refresh process, the concentrated refresh process, and the second distributed refresh process in the case where a third mode has been set.