IP Library Granted Patent US 8,473,655
Granted Patent B2
US 8,473,655 · App. 13/007,687 · Granted Jun 25, 2013

Method and apparatus for dividing a single serial enclosure management bit stream into multiple enclosure management bit streams and for providing the respective bit streams to respective midplanes

Inventors: Jason M. Stuhlsatz (Dacula, GA); Naman Nair (Fremont, CA); Debal Krishna Mridha (Bangalore, IN); Lakshmana Anupindi (Suwanee, GA); Kakanuru Lakshmi Kanth Reddy (Bangalore, IN)
Assignee: LSI Corporation
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Quick Facts
Patent No.
US 8,473,655
App. No.
13/007,687
Granted
Jun 25, 2013
Kind
B2
Abstract

A controller is provided that receives a single enclosure management (EM) serial bit stream from an expander or other device and divides the EM serial bit stream into multiple EM serial bit streams for delivery to multiple respective midplanes or backplanes. In this way, a separate EM serial bit stream is provided to each midplane or backplane without having to increase the number of ports that are available on the expander or other device that interfaces with the backplane or midplane.

Claims (38)

1. An apparatus for dividing an enclosure management (EM) serial bit stream into a plurality of EM serial bit streams, the apparatus comprising:

a controller having at least a first EM input port for receiving an input EM serial bit stream and N EM output ports for outputting N EM serial bit streams from the controller, where N is a positive integer that is equal to or greater than 2; and

at least a first EM separator within the controller that divides the input EM serial bit stream into N EM serial bit streams and causes each of the N EM serial bit streams to be output from the controller via a respective one of the N EM output ports to N respective midplanes each having at least one respective disk drive attached thereto.

2. The apparatus of claim 1 , wherein the input EM serial bit stream is a Serial General Purpose Input/Output (SGPIO) bit stream and wherein the N EM serial bit streams are SGPIO bit streams, each of the N SGPIO bit streams comprising SGPIO bits associated with at least said at least one disk drive attached to the respective midplane.

3. The apparatus of claim 2 , wherein each of the N SGPIO bit streams comprises SGPIO bits associated with said at least one disk drive attached to the respective midplane and SGPIO bits associated with higher-numbered disk drives attached to higher-numbered midplanes.

4. The apparatus of claim 1 , wherein the input EM serial bit stream is an Inter-Integrated Circuit (I 2 C) bit stream and wherein the N EM serial bit streams are I 2 C bit streams, each of the N I 2 C bit streams comprising I 2 C bits associated with said at least one disk drive attached to the respective midplane.

5. The apparatus of claim 4 , wherein each of the N I 2 C bit streams comprises I 2 C bits associated with said at least one disk drive attached to the respective midplane and I 2 C bits associated with higher-numbered disk drives attached to higher-numbered midplanes.

6. The apparatus of claim 1 , wherein the input EM serial bit stream is sent to the controller by an expander.

7. The apparatus of claim 1 , wherein the input EM serial bit stream is sent to the controller by a host bus adapter (HBA).

8. The apparatus of claim 1 , wherein the input EM serial bit stream is sent to the controller by a Redundant Array of Inexpensive Disk (RAID) adapter.

9. The apparatus of claim 1 , further comprising:

N fault header output ports for outputting N drive signals for driving N fault light-emitting diodes (LEDs), and wherein the first EM separator also identifies N fault bits associated with the N midplanes and produces the N drive signals from the N fault bits, respectively, and causes the N drive signals to be output from the N fault header output ports, respectively.

10. An apparatus for dividing one or more enclosure management (EM) serial bit streams into a plurality of EM serial bit streams, the apparatus comprising:

a controller having at least first and second EM input ports for receiving a first input EM serial bit stream of a first EM type and second input EM bits of a second type, respectively, the controller having N EM output ports for outputting N EM serial bit streams from the controller, where N is a positive integer that is equal to or greater than 2 and

at least a first EM separator within the controller that divides the first input EM serial bit streams into N EM serial bit streams of the first and second type;

at least a first connection manager that manages connections between the second EM input port and other elements of the controller; and

N multiplexors (MUXes) within the controller, each MUX having at least first and second input terminals, an output terminal, and a selection terminal, the first and second input terminals of each MUX receiving one of the N EM bits of the first type and one of the N EM bits of the second type, respectively, each of the MUXes receiving a respective selection bit from a respective midplane at the respective selection terminal and causing either the EM bit of the first type at the first input terminal or the EM bit of the second type at the second input terminal to be output from the respective MUX on the respective output terminal based on whether or not the respective selection bit is asserted, and wherein the EM serial bits that are output on the output terminals of the MUXes are output from the controller via respective EM output ports of the controller and provided to N respective midplanes.

11. The apparatus of claim 10 , wherein the first type is a Serial General Purpose Input/Output (SGPIO) type and wherein the second type is an I 2 C type.

12. The apparatus of claim 11 , wherein each of the N EM serial bit streams comprises bits associated with said at least one disk drive attached to the respective midplane and bits associated with higher-numbered disk drives attached to higher-numbered midplanes.

13. A method for dividing an enclosure management (EM) serial bit stream into a plurality of EM serial bit streams, the method comprising:

in a controller, receiving an input EM serial bit stream;

in the controller, dividing the input EM serial bit stream into N EM serial bit streams, where N is a positive integer that is equal to or greater than 2; and

in the controller, causing each of the N EM serial bit streams to be provided via a respective EM output port of the controller to a respective midplane of the N respective midplanes, wherein each of the midplanes has at least one respective disk drive attached thereto.

14. The method of claim 13 , wherein the input EM serial bit stream is a Serial General Purpose Input/Output (SGPIO) bit stream and wherein the N EM serial bit streams are SGPIO bit streams, each of the N SGPIO bit streams comprising at least SGPIO bits associated with at least said at least one disk drive attached to the respective midplane.

15. The method of claim 14 , wherein each of the N SGPIO bit streams comprises SGPIO bits associated with said at least one disk drive attached to the respective midplane and SGPIO bits associated with higher-numbered disk drives attached to higher-numbered midplanes of the N midplanes.

16. The method of claim 10 , wherein the input EM serial bit stream is sent to the controller by an expander.

17. The method of claim 10 , wherein the input EM serial bit stream is sent to the controller by a host bus adapter (HBA).

18. The method of claim 10 , wherein the input EM serial bit stream is sent to the controller by a Redundant Array of Inexpensive Disk (RAID) adapter.

19. The method of claim 10 , further comprising:

in the first EM separator, identifying N fault bits associated with the N midplanes, respectively, and producing N drive signals from the N fault bits, respectively, and causing the N drive signals to be output from N fault header output ports, respectively, of the controller.

20. A method for dividing an enclosure management (EM) serial bit stream into a plurality of EM serial bit streams, the method comprising:

in a controller, receiving a first input EM serial bit stream of a first type and second EM bits of a second type;

with a first EM separator of the controller, dividing the first input EM serial bit stream into N EM serial bit streams of the first type;

in the controller, providing the EM bits of the N EM serial bit streams of the first type to first input terminals of N multiplexors (MUXes) of the controller and providing the EM bits of the second type to second input terminals of the N MUXes;

in the controller, providing respective selection bits received from N respective midplanes to respective selector terminals of the respective MUXs; and

in each respective MUX, based on whether or not the respective selection bit is asserted, causing either the EM bit of the EM serial bit stream of the first type at the respective first input terminal of the respective MUX or the EM bit of the second type at the respective second input terminal of the respective MUX to be output from the respective MUX on the respective output terminal, and wherein the EM bits that are output on the output terminals of the MUXes are output from the controller via respective EM output ports of the controller and provided to the N respective midplanes.

21. The method of claim 20 , wherein the first type is a Serial General Purpose Input/Output (SGPIO) type and wherein the second type is an Inter-Integrated Circuit (I 2 C) type.

22. The method of claim 20 , wherein each of the N EM serial bit streams comprises bits associated with said at least one disk drive attached to the respective midplane and bits associated with higher-numbered disk drives attached to higher-numbered midplanes.

Assignments (8)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 17, 2011
From: STUHLSATZ, JASON MICHAEL; NAIR, NAMAN; MRIDHA, DEBAL KRISHNA; ANUPINDI, LAKSHMANA; REDDY, KAKANURU LAKSHMI KANTH
To: LSI CORPORATION
Reel/Frame 025739/0550 →
Continuity (1)
Related Publication 20120185626A1 · Jul 19, 2012