Data synchronizer for synchronizing data and communication interface including the same

1. A data synchronizer comprising:

a data hold module configured to receive first data synchronized with a first clock signal on the basis of a second timing signal and output second data obtained by synchronizing the received first data with a second clock signal differing from the first clock signal in frequency;

a reception timing generation module configured to generate a timing signal synchronized with the second clock signal as the second timing signal on the basis of a first timing signal corresponding to the first data and synchronized with the first clock signal, the reception timing generation module comprising flip-flops connected in cascade; and

an update timing adjusting module configured to limit the timing to update the flip-flops in value on the basis of an update enable signal synchronized with the second clock signal.

2. The data synchronizer of claim 1 , wherein:

the update enable signal is asserted once in a plurality of cycles of the second clock signal; and

the update timing adjusting module is configured to permit the update of the values of the flip-flops in a cycle of the second clock signal in which the update enable signal is asserted.

3. The data synchronizer of claim 2 , wherein the reception timing generation module further comprises:

a first logic gate configured to detect a state where the output of the last-stage one of the flip-flops and the output of a flip-flop in a stage preceding the last stage differ in value from each other for the first time after the timing shown by the first timing signal; and

a second logic gate configured to output the output signal of the first logic gate as the second timing signal during a period when the update enable signal is asserted.

4. The data synchronizer of claim 3 , wherein the update timing adjusting module comprises selectors corresponding to the flip-flops respectively, each of the selectors being configured to select a signal used to update the value of the corresponding one of the flip-flops and output the selected signal to the corresponding flip-flop during a period when the update enable signal is asserted.

5. A communication interface comprising:

a first data synchronizer configured to synchronize first data synchronized with a first clock signal with a second clock signal differing from the first clock signal in frequency; and

a second data synchronizer configured to synchronize third data synchronized with a third clock with a fourth clock signal differing from the third clock signal in frequency and phase and coinciding with the second clock signal in frequency and phase, and

wherein the first data synchronizer comprises:

a first hold module configured to receive the first data on the basis of a second timing signal and output second data obtained by synchronizing the received first data with the second clock signal;

a first reception timing generation module configured to generate a timing signal synchronized with the second clock signal as the second timing signal on the basis of a first timing signal corresponding to the first data and synchronized with the first clock signal, the first reception timing generation module comprising first flip-flops connected in cascade; and

a first update timing adjusting module configured to limit the timing to update the first flip-flops in value on the basis of a first update enable signal synchronized with the second clock signal, and

wherein the second data synchronizer comprises:

a second data hold module configured to receive the third data on the basis of a fourth timing signal and output fourth data obtained by synchronizing the received third data with the fourth clock signal;

a second reception timing generation module configured to generate a timing signal synchronized with the fourth clock signal as the fourth timing signal on the basis of a third timing signal corresponding to the third data and synchronized with the third clock signal, the second reception timing generation module comprising second flip-flops connected in cascade; and

a second update timing adjusting module configured to limit the timing to update the second flip-flops in value on the basis of a second update enable signal synchronized with the fourth clock signal.

6. The communication interface of claim 5 , further comprising a clock generation module configured to generate the second clock signal and the fourth clock signal independently.

7. The communication interface of claim 5 , wherein the second clock signal is used as the fourth clock signal.

8. A data synchronizer comprising:

a reception module configured to receive first data synchronized with a first clock signal;

a generation module configured to generate a second timing signal synchronized with a second clock signal differing from the first clock signal in frequency based on a first timing signal and an enable signal, wherein the first timing signal is synchronized with the first clock signal, and the enable signal is synchronized with the second clock signal and corresponds to the first clock signal; and

an output module configured to output second data synchronized with the second clock signal and the generated second timing signal from the received first data.

9. A communication device comprising a controller configured to transmit and to receives data to and from a host, wherein the controller comprises the data synchronizer of claim 8 .