Memory array of floating gate-based non-volatile memory cells

1. A memory array comprising:

a plurality of memory cells organized in a matrix of rows and columns, each of the memory cells comprising:

a high voltage access transistor;

a floating gate memory transistor electrically connected to the access transistor; and

a coupling capacitor electrically connected to the memory transistor;

a first set of word lines each electrically connected to the coupling capacitor in each of the memory cells in a respective row;

a second set of word lines each electrically connected to the access transistor in each of the memory cells in a respective row;

a first set of bit lines each electrically connected to the access transistor in each of the memory cells in a respective column;

a second set of bit lines each electrically connected to the memory transistor in each of the memory cells in a respective column, the second set of bit lines each electrically connected together;

a plurality of column address transistors each electrically connected to a bit line in the first set of bit lines;

a single voltage supply point electrically connected to the second set of bit lines;

a program charge pump electrically connected to the voltage supply point; and

an erase charge pump electrically connected to the voltage supply point;

wherein various combinations of voltages can be applied to the word lines and the bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

2. The memory array of claim 1 , wherein the memory cells are organized in a two-dimensional array.

3. The memory array of claim 1 , wherein the program operation is carried out by programming from impact ionization generated electrons, and the erase operation is carried out by Fowler-Nordheim tunneling.

4. The memory array of claim 1 , wherein the single point voltage supply is configured to apply programming and erasure voltages.

5. The memory array of claim 1 , wherein the access transistors comprise symmetrical NDMOS devices.

6. The memory array of claim 1 , wherein the program charge pump is configured to generate a programming voltage.

7. The memory array of claim 1 , wherein the erase charge pump is configured to generate an erasure voltage.

8. The memory array of claim 1 , wherein the program charge pump and the erase charge pump are constructed entirely of low voltage devices.

9. The memory array of claim 1 , wherein the high voltage access transistor comprises a gate oxide layer having a thickness of about 10-15 nm.

10. The memory array of claim 1 , wherein the floating gate memory transistor comprises a gate oxide layer having a thickness of about 10-15 nm.

11. The memory array of claim 1 , wherein the coupling capacitor comprises a gate oxide layer having a thickness of about 10-15 nm.