Memory array of floating gate-based non-volatile memory cells

1. A method of erasing a single bit in a memory cell of a memory array, the method comprising:

grounding a word line, in a first set of word lines, connected to the memory cell to be erased, wherein the memory cell is one of a plurality of memory cells organized in a matrix of rows and columns, each of the memory cells comprising:

an access transistor;

a floating gate memory transistor electrically connected to the access transistor; and

a coupling capacitor electrically connected to the memory transistor;

grounding a word line, in a second set of word lines, connected to the memory cell to be erased;

applying a first voltage to a bit line connected to the memory cell to be erased; and

applying a second voltage to word lines, in the first set of word lines, not connected to the memory cell to be erased, the second voltage being about one-half of the first voltage.

2. The method of claim 1 , wherein the memory cells are organized in a two-dimensional array.

3. The method of claim 1 , wherein the memory cells each comprise a capacitor terminal electrically connected to the coupling capacitor, a program terminal electrically connected to the memory transistor, and a control terminal electrically connected to the access transistor.

4. The method of claim 1 , wherein the high voltage access transistor comprises a gate oxide layer having a thickness of up to about 20 nm.

5. The method of claim 1 , wherein the floating gate memory transistor comprises a gate oxide layer having a thickness of up to about 20 nm.

6. The method of claim 1 , wherein the coupling capacitor comprises a gate oxide layer having a thickness of up to about 20 nm.

7. The method of claim 1 , wherein:

the first set of word lines is electrically connected to the coupling capacitor in each of the memory cells in a respective row;

the second set of word lines is electrically connected to the access transistor in each of the memory cells in a respective row;

the first set of bit lines is electrically connected to the access transistor in each of the memory cells in a respective column; and

the second set of bit lines is electrically connected to the memory transistor in each of the memory cells in a respective column.

8. The method of claim 1 , wherein the erasing is carried out by Fowler-Nordheim tunneling.

9. The method of claim 1 , wherein the first voltage is sufficient to form an electric field to induce Fowler-Nordheim tunneling.

10. The method of claim 1 , wherein the first voltage is about 14-22 volts.

11. A method of erasing a single bit in a memory cell of a memory array, the method comprising:

providing a memory array comprising:

a plurality of memory cells organized in a matrix of rows and columns, each of the memory cells comprising:

a high voltage access transistor;

a floating gate memory transistor electrically connected to the access transistor; and

a coupling capacitor electrically connected to the memory transistor;

a first set of word lines each electrically connected to the coupling capacitor in each of the memory cells in a respective row;

a second set of word lines each electrically connected to the access transistor in each of the memory cells in a respective row;

a first set of bit lines each electrically connected to the access transistor in each of the memory cells in a respective column;

a second set of bit lines each electrically connected to the memory transistor in each of the memory cells in a respective column, the second set of bit lines each electrically connected together;

a plurality of column address transistors each electrically connected to a bit line in the first set of bit lines;

a single voltage supply point electrically connected to the second set of bit lines;

a program charge pump electrically connected to the voltage supply point; and

an erase charge pump electrically connected to the voltage supply point;

applying an erase voltage to the voltage supply point;

grounding a word line, in the first set of word lines, connected to the capacitor of the memory cell to be erased;

grounding a word line, in the second set of word lines, connected to the access transistor of the memory cell to be erased;

applying a first voltage to word lines, in the first set of word lines, not connected to the memory cell to be erased;

applying a second voltage to word lines, in the second set of word lines, not connected to the memory cell to be erased, the second voltage equal to the first voltage; and

grounding a column address transistor in a column supporting the memory cell to be erased.

12. The method of claim 11 , wherein the memory cells are organized in a two-dimensional array.

13. The method of claim 11 , wherein the memory cells each comprise a capacitor terminal electrically connected to the coupling capacitor, a program terminal electrically connected to the memory transistor, and a control terminal electrically connected to the access transistor.

14. The method of claim 11 , wherein the high voltage access transistor comprises a gate oxide layer having a thickness of about 10-15 nm.

15. The method of claim 11 , wherein the floating gate memory transistor comprises a gate oxide layer having a thickness of about 10-15 nm.

16. The method of claim 11 , wherein the coupling capacitor comprises a gate oxide layer having a thickness of about 10-15 nm.

17. The method of claim 11 , wherein the erasing is carried out by Fowler-Nordheim tunneling.

18. The method of claim 11 , wherein the first voltage is sufficient to form an electric field to induce Fowler-Nordheim tunneling.

19. The method of claim 11 , wherein the first voltage is about 14-22 volts.

20. The method of claim 11 , wherein the erase voltage is provided by the erase charge pump.