Reduced pixel area image sensor
View Patent ↗An image sensor that includes a plurality of pixels disposed on a substrate, each pixel includes at least one photosensitive region that collects charges in response to incident light; a charge-to-voltage conversion node for sensing the charge from the at least one photosensitive region and convening the charge to a voltage; an amplifier transistor having a source connected to an output node, having a gate connected to the charge-to-voltage conversion node and having a drain connected to at least a portion of a power supply node; and a reset transistor connecting the output node and the charge-to-voltage conversion node.
1. A method for reading out charge from a row of pixels in an image sensor, wherein each pixel in the row includes a photodetector, a floating diffusion, and each column output line in the image sensor is connected to a load transistor, the method comprising:
turning off the load transistors;
setting the column output lines to a first voltage level;
resetting the floating diffusions by pulsing reset transistors in the pixels in the row to be read out, wherein pulsing the reset transistors transfers the first voltage level on the column output lines to the floating diffusions;
turning on the load transistors and setting the column output lines to a second voltage level; and
reading out signals from the pixels in the row.
2. The method as in claim 1 , wherein reading out signals from the pixels in the row comprises:
reading out reset signals on the floating diffusions in the row;
transferring charge from the photodetectors to the floating diffusions in the row by pulsing the transfer gates in the row;
reading out image signals on the floating diffusions in the row; and
turning on the reset transistors in the pixels in the row.
3. The method of claim 1 , wherein setting the column output lines to the first voltage level includes turning a switch connected to the column output lines to the first voltage level, and wherein setting the column output lines to the second voltage level includes turning the switch to an open setting and allowing the column output lines to be driven by output transistors that have gates coupled to the floating diffusions.
4. The method of claim 3 , wherein the output transistors share a power supply node with at least one of the output transistors in the row.