Semiconductor device and structure
View Patent ↗A semiconductor device including a first layer including first transistors, wherein first logic circuits are constructed by the first transistors, and wherein the first logic circuits include at least one of Inverter, NAND gate, or NOR gate; and a second layer overlaying said first layer, the second layer including second transistors, wherein second logic circuits are constructed by the second transistors; wherein each logic circuit in the first logic circuits has inputs and at least one first output, the inputs are connected to the second logic circuits; wherein each logic circuit in the second logic circuits has a second output, and wherein the first transistors include first selectors adapted to selectively replace at least one of the at least one first outputs with at least one of the second outputs.
1. A semiconductor device comprising:
a first layer comprising a plurality of first transistors, wherein said plurality of first transistors construct a plurality of first logic circuits, and wherein said plurality of first logic circuits comprise a plurality of flip-flops; and
a second layer overlaying said first layer, said second layer comprising a plurality of second transistors, wherein said second transistors are mono-crystal transistors;
wherein said plurality of second transistors construct a plurality of second logic circuits;
wherein each logic circuit in said plurality of first logic circuits has at least one first output,
wherein each logic circuit in said plurality of second logic circuits has a second output, and wherein said plurality of first transistors comprise a plurality of first selectors adapted to selectively replace at least one of said first outputs with at least one of said second outputs.
2. A semiconductor device according to claim 1 , wherein said second layer has a thickness less than 1 micron.
3. A semiconductor device according to claim 1 , wherein each logic circuit in said plurality of first logic circuits has at least one input coupled to an input to one of said second logic circuits.
4. A semiconductor device according to claim 1 , further comprising:
a plurality of circuits adapted to perform a comparison between one of said first outputs and one of said second outputs.
5. A semiconductor device according to claim 1 , wherein said at least one first output is either an output of a flip-flop or an input of a flip-flop.
6. A semiconductor device according to claim 1 , further comprising:
a controller adapted to perform testing of said semiconductor device.
7. A semiconductor device comprising:
a first layer comprising a plurality of first transistors, wherein said plurality of first transistors construct a plurality of first logic circuits, and wherein said plurality of first logic circuits comprise a plurality of flip-flops; and
a second layer overlaying said first layer, said second layer comprising a plurality of second transistors, wherein said second transistors are mono-crystal transistors;
wherein said plurality of second transistors construct a plurality of second logic circuits;
wherein at least one of said plurality of first logic circuits includes a selector adapted to replace said at least one of said plurality of first logic circuits with one of said plurality of second logic circuits to repair operation of said semiconductor device.
8. A semiconductor device according to claim 7 , wherein said second layer has a thickness less than 1 micron.
9. A semiconductor device according to claim 7 , wherein said first layer comprises a plurality of flip-flops and each flip-flop in said plurality of flip-flops has an input and an output, wherein either said input or output is selectively coupleable to said second layer.
10. A semiconductor device according to claim 7 , further comprising:
a plurality of circuits each adapted to perform a comparison between a signal generated by said first layer and a signal generated by said second layer.
11. A semiconductor device according to claim 7 , wherein said first layer comprises a plurality of flip-flops and each flip-flop in said plurality of flip-flops has a selectively coupleable additional input generated by said second transistor.
12. A semiconductor device according to claim 7 , further comprising:
a controller adapted to perform testing of said semiconductor device.
13. A semiconductor device comprising:
a first layer comprising a plurality of first transistors constructing logic circuits; and
a second layer comprising a plurality of second transistors, wherein said second transistors are mono-crystal transistors;
wherein said plurality of second transistors overlays said plurality of first transistors and construct redundancy circuits for said logic circuits of said plurality of first transistors; and
wherein said first layer comprises a plurality of flip-flops and each flip-flop in said plurality of flip-flops has an input and an output, wherein either said input or said output is selectively coupleable to said second layer.
14. A semiconductor device according to claim 13 , wherein fabrication of said device comprises layer transfer.
15. A semiconductor device according to claim 13 , further comprising:
a plurality of circuits each adapted to perform a comparison between a signal generated by said first layer and a signal generated by said second layer.
16. A semiconductor device according to claim 13 , wherein said first layer comprises a plurality of flip-flops and each flip-flop in said plurality of flip-flops has a selectively coupleable additional input generated by said second transistor.
17. A semiconductor device according to claim 13 , further comprising:
a controller adapted to perform testing of said semiconductor device.