Switchable capacitive element with improved quality factor, and method of production
View Patent ↗A switchable capacitive element having an adjustable capacitance and an improved quality factor is specified. To this end, the characteristic variables of the switchable capacitive element are optimized in accordance with the equations cited in the description.
1. A switchable capacitive element (SKE), comprising
n parallel-connected paths (PF) with a respective capacitor (K) of capacitance C,
per path n semiconductor switches (SW), cascaded in the path, with a respective source connection (S), gate connection (G) and drain connection (D),
wherein
the switchable capacitive element (SKE) has a frequency-dependent quality factor Q S on (ω) when the semiconductor switches (SW) are open and has a frequency-dependent quality factor Q S off (ω) when the semiconductor switches (SW) are closed,
R G is the nonreactive resistance of a resistive element connected to the gate connection, R GS is the nonreactive resistance between the gate connection (G) and the source connection (S), R GD is the nonreactive resistance between the gate connection (G) and the drain connection (D), R D is the nonreactive resistance of a capacitive element connected between the drain connection (D) and the source connection (S), r DS is the nonreactive resistance between the drain connection (D) and the source connection (S),
C GD is the capacitance between the gate connection (G) and the drain connection (D), C GS is the capacitance between the gate connection (G) and the source connection (S), C DS is the capacitance between the drain connection (D) and the source connection (S),
wherein the values C, R MIM , R ON , R G , R GS , R GD , R D , r DS , C GD , C GS , C DS are optimized according to the equation
Q
ON
S
=
1
ω
·
(
R
MIM
+
n
·
R
ON
R
a
n
·
R
ON
+
R
a
)
·
C
when the semiconductor switches (SW) are open and according to the equation
Q
OFF
S
=
1
ω
·
(
R
MIM
+
n
R
d
+
n
ω
2
C
d
2
R
e
+
n
3
ω
2
C
d
2
R
a
)
·
C
d
C
C
d
+
n
C
when the semiconductor switches (SW) are closed, wherein
R
a
=
R
G
·
C
GD
+
C
GS
C
GD
R
d
=
R
c
(
1
+
C
DS
C
c
)
2
C
d
=
C
DS
+
C
c
R
e
=
r
DS
R
D
r
DS
+
R
D
R
c
=
R
GD
1
+
(
ω
R
GD
C
GD
)
2
+
R
GS
1
+
(
ω
R
GS
C
GS
)
2
-
1
ω
2
R
G
C
GD
C
GS
C
c
=
C
GD
C
GS
C
GD
+
C
GS
and n is a natural number ≧1.
2. The switchable capacitive element (SKE) according to claim 1 , wherein the cascade of the semiconductor switches (SW) in each path (PF) is connected between the capacitor (K) of the path (PF) and ground.
3. The switchable capacitive element (SKE) according to claim 1 , wherein the values C, R MIM , R ON , R G , R GS , R GD , R D , r DS , C GD , C GS and C DS are chosen such that the ratio
Q
C
GD
+
C
GS
+
C
DS
comprising the quality factor Q and the sum of the intrinsic capacitances C GD , C GS and C DS is at a maximum.
4. A switchable capacitive element, comprising
n parallel-connected paths (PF) with a respective capacitor (K) of capacitance C,
per path (PF) n semiconductor switches (SW), cascaded in the path (PF), with a respective source connection (S), gate connection (G) and drain connection (D),
wherein
the switchable capacitive element (SKE) has a frequency-dependent quality factor Q D on (ω) when the semiconductor switches (SW) are open and has a frequency-dependent quality factor Q D off (ω) when the semiconductor switches (SW) are closed,
R G is the nonreactive resistance of a resistive element connected to the gate connection (G), R GS is the nonreactive resistance between the gate connection (G) and the source connection (S), R GD is the nonreactive resistance between the gate connection (G) and the drain connection (D), R D is the nonreactive resistance of a resistive element connected between the drain connection (D) and the source connection (S), r DS is the nonreactive resistance of the switch between the drain connection (D) and the source connection (S),
C GD is the capacitance between the gate connection (G) and the drain connection (D), C GS is the capacitance between the gate connection (G) and the source connection (S), C DS is the capacitance between the drain connection (D) and the source connection (S),
wherein the values C, R MIM , R ON , R G , R GS , R GD , R D , r DS , C GD , C GS , C DS are optimized according to the equation
Q
ON
D
=
1
ω
·
(
R
MIM
+
n
R
ON
+
n
ω
2
C
2
R
a
+
n
ω
2
C
2
R
b
)
·
C
when the semiconductor switches (SW) are open and according to the equation
Q
OFF
D
=
1
ω
·
(
R
MIM
+
n
R
d
+
n
ω
2
C
d
2
R
e
+
n
ω
2
C
2
R
a
+
n
ω
2
(
C
C
d
n
C
+
C
d
)
2
R
b
)
·
C
C
d
n
C
+
C
d
when the semiconductor switches (SW) are closed, wherein
R
a
=
R
G
·
C
GD
+
C
GS
C
GD
R
b
=
R
G
·
C
GD
+
C
GS
C
GS
R
d
=
R
c
(
1
+
C
DS
C
c
)
2
C
d
=
C
DS
+
C
c
R
e
=
r
DS
R
D
r
DS
+
R
D
R
c
=
R
GD
1
+
(
ω
R
GD
C
GD
)
2
+
R
GS
1
+
(
ω
R
GS
C
GS
)
2
-
1
ω
2
R
G
C
GD
C
GS
C
c
=
C
GD
C
GS
C
GD
+
C
GS
and n is a natural number ≧1.
5. The switchable capacitive element (SKE) according to claim 4 , wherein the capacitor (K) of each path (PF) is connected between the cascade of the semiconductor switches (SW) and ground.
6. The switchable capacitive element (SKE) according to claim 4 , wherein the values C, R MIM , R ON , R G , R GS , R GD , R D , r DS , C GD , C GS and C DS are chosen such that the ratio
Q
C
GD
+
C
GS
+
C
DS
comprising the quality factor Q and the sum of the intrinsic capacitances C GD , C GS and C DS is at a maximum.
7. A switchable capacitance bank (SKB) having m switchable capacitive elements (SKE), wherein each of the switchable capacitive elements (SKE) comprises
n parallel-connected paths (PF) with a respective capacitor (K) of capacitance a m *C and per path (PF) n semiconductor switches (SW), cascaded in the path (PF), with a respective source connection (S), gate connection (G) and drain connection (D),
wherein
the capacitors (K) of each path (PF) are connected between the cascade of the semiconductor switches (SW) and ground,
the switchable capacitive element (SKE) has a frequency-dependent quality factor Q on (ω) when the semiconductor switches (SW) are open and has a frequency-dependent quality factor Q off (ω) when the semiconductor switches (SW) are closed,
R G is the nonreactive resistance of a resistive element connected to the gate connection (G), R GS is the nonreactive resistance between the gate connection (G) and the source connection (S), R GD is the nonreactive resistance between the gate connection (G) and the drain connection (D), R D is the nonreactive resistance of a resistive element connected between the drain connection (D) and the source connection (S), r DS is the nonreactive resistance between the drain connection (D) and the source connection (S),
C GD is the capacitance between the gate connection (G) and the drain connection (D), C GS is the capacitance between the gate connection (G) and the source connection (S), C DS is the capacitance between the drain connection (D) and the source connection (S),
wherein the values C, R MIM , R ON , R G , R GS , R GD , R D , r DS , C GD , C GS , C DS are optimized according to the equation
Q
ON
=
1
ω
·
(
1
a
R
MIM
+
n
·
1
a
R
ON
·
1
a
·
R
a
n
·
1
a
R
ON
+
1
a
R
a
)
·
a
·
C
when the semiconductor switches (SW) are open and according to the equation
Q
OFF
=
1
ω
·
(
1
a
R
MIM
+
n
1
a
R
d
+
n
ω
2
a
2
C
d
2
1
a
R
e
+
n
3
ω
2
a
2
C
d
2
1
a
R
a
)
·
a
C
d
·
a
·
C
a
C
d
+
n
·
a
2
C
when the semiconductor switches (SW) are closed, wherein
R
a
=
R
G
·
C
GD
+
C
GS
C
GD
R
b
=
R
G
·
C
GD
+
C
GS
C
GS
R
d
=
R
c
(
1
+
C
DS
C
c
)
2
C
d
=
C
DS
+
C
c
R
e
=
r
DS
R
D
r
DS
+
R
D
R
c
=
R
GD
1
+
(
ω
R
GD
C
GD
)
2
+
R
GS
1
+
(
ω
R
GS
C
GS
)
2
-
1
ω
2
R
G
C
GD
C
GS
C
c
=
C
GD
C
GS
C
GD
+
C
GS
and n is a natural number ≧1, m is an integer ≧0 and <n and a is a real number >1.
8. The switchable capacitance bank (SKB) according to claim 7 , wherein the values C, R MIM , R ON , R G , R GS , R GD , R D , r DS , C GS , C GS and C DS are chosen such that the ratio
Q
C
GD
+
C
GS
+
C
DS
comprising the quality factor Q and the sum of the intrinsic capacitances C GD , C GS and C DS is at a maximum.
9. A method for producing adjustable capacitive elements or capacitance banks arranged in n parallel-connected paths with a respective capacitor having a capacitance a m *C, where a is a real or natural number greater than one and m is an integer number greater than or equal to zero and less than n, each path including a semiconductor switch cascaded in the path with a respective source connection (S), gate connection (G), and drain connection (D), the method comprising:
predetermining a target quality factor for the element or the bank;
ascertaining the magnitude of the capacitances of the capacitors of the paths; and
optimizing the target quality factor according to a function that includes a resistance R a whose value is calculated from a nonreactive resistance R G of an external resistive element connected to the gate connection (G), a gate-drain capacitance C GD between the gate connection and the drain connection, and a gate-source capacitance C GS between the gate connection and the source connection.
10. The method of claim 9 , wherein
the switchable capacitive element (SKE) has a frequency-dependent quality factor Q S on (ω) when the semiconductor switches (SW) are open and has a frequency-dependent quality factor Q S off (ω) when the semiconductor switches (SW) are closed,
R G is the nonreactive resistance of a resistive element connected to the gate connection, R GS is the nonreactive resistance between the gate connection (G) and the source connection (S), R GD is the nonreactive resistance between the gate connection (G) and the drain connection (D), R D is the nonreactive resistance of a capacitive element connected between the drain connection (D) and the source connection (S), r DS is the nonreactive resistance between the drain connection (D) and the source connection (S),
C GD is the capacitance between the gate connection (G) and the drain connection (D), C GS is the capacitance between the gate connection (G) and the source connection (S), C DS is the capacitance between the drain connection (D) and the source connection (S),
wherein the values C, R MIM , R ON , R G , R GS , R GD , R D , r DS , C GD , C GS , C DS are optimized according to the equation
Q
ON
S
=
1
ω
·
(
R
MIM
+
n
·
R
ON
R
a
n
·
R
ON
+
R
a
)
·
C
when the semiconductor switches (SW) are open and according to the equation
Q
OFF
S
=
1
ω
·
(
R
MIM
+
n
R
d
+
n
ω
2
C
d
2
R
e
+
n
3
ω
2
C
d
2
R
a
)
·
C
d
C
C
d
+
n
C
when the semiconductor switches (SW) are closed, wherein
R
a
=
R
G
·
C
GD
+
C
GS
C
GD
R
d
=
R
c
(
1
+
C
DS
C
c
)
2
C
d
=
C
DS
+
C
c
R
e
=
r
DS
R
D
r
DS
+
R
D
R
c
=
R
GD
1
+
(
ω
R
GD
C
GD
)
2
+
R
GS
1
+
(
ω
R
GS
C
GS
)
2
-
1
ω
2
R
G
C
GD
C
GS
C
c
=
C
GD
C
GS
C
GD
+
C
GS
and n is a natural number ≧1.
11. The method of claim 9 , wherein the cascade of the semiconductor switches (SW) in each path (PF) is connected between the capacitor (K) of the path (PF) and ground.
12. The method of claim 9 , wherein the values C, R MIM , R ON , R G , R GS , R GD , R D , r DS , C GD , C GS and C DS are chosen such that the ratio
Q
C
GD
+
C
GS
+
C
DS
comprising the quality factor Q and the sum of the intrinsic capacitances C GD , C GS and C DS is at a maximum.
13. The method of claim 9 , wherein
the switchable capacitive element (SKE) has a frequency-dependent quality factor Q D on (ω) when the semiconductor switches (SW) are open and has a frequency-dependent quality factor Q D off (ω) when the semiconductor switches (SW) are closed,
R G is the nonreactive resistance of a resistive element connected to the gate connection (G), R GS is the nonreactive resistance between the gate connection (G) and the source connection (S), R GD is the nonreactive resistance between the gate connection (G) and the drain connection (D), R D is the nonreactive resistance of a resistive element connected between the drain connection (D) and the source connection (S), r DS is the nonreactive resistance of the switch between the drain connection (D) and the source connection (S),
C GD is the capacitance between the gate connection (G) and the drain connection (D), C GS is the capacitance between the gate connection (G) and the source connection (S), C DS is the capacitance between the drain connection (D) and the source connection (S),
wherein the values C, R MIM , R ON , R G , R GS , R GD , R D , r DS , C GD , C GS , C DS are optimized according to the equation
Q
ON
D
=
1
ω
·
(
R
MIM
+
n
R
ON
+
n
ω
2
C
2
R
a
+
n
ω
2
C
2
R
b
)
·
C
when the semiconductor switches (SW) are open and according to the equation
Q
OFF
D
=
1
ω
·
(
R
MIM
+
n
R
d
+
n
ω
2
C
d
2
R
e
+
n
ω
2
C
2
R
a
+
n
ω
2
(
C
C
d
nC
+
C
d
)
2
R
b
)
·
C
C
d
nC
+
C
d
when the semiconductor switches (SW) are closed, wherein
R
a
=
R
G
·
C
GD
+
C
GS
C
GD
R
b
=
R
G
·
C
GD
+
C
GS
C
GS
R
d
=
R
c
(
1
+
C
DS
C
c
)
2
C
d
=
C
DS
+
C
c
R
e
=
r
DS
R
D
r
DS
+
R
D
R
c
=
R
GD
1
+
(
ω
R
GD
C
GD
)
2
+
R
GS
1
+
(
ω
R
GS
C
GS
)
2
-
1
ω
2
R
G
C
GD
C
GS
C
c
=
C
GD
C
GS
C
GD
+
C
GS
and n is a natural number ≧1.
14. The method of claim 9 , wherein the n parallel-connected paths (PF) have a respective capacitor (K) of capacitance a m *C, and wherein
the capacitors (K) of each path (PF) are connected between the cascade of the semiconductor switches (SW) and ground,
the switchable capacitive element (SKE) has a frequency-dependent quality factor Q on (ω) when the semiconductor switches (SW) are open and has a frequency-dependent quality factor Q off (ω) when the semiconductor switches (SW) are closed,
R G is the nonreactive resistance of a resistive element connected to the gate connection (G), R GS is the nonreactive resistance between the gate connection (G) and the source connection (S), R GD is the nonreactive resistance between the gate connection (G) and the drain connection (D), R D is the nonreactive resistance of a resistive element connected between the drain connection (D) and the source connection (S), r DS is the nonreactive resistance between the drain connection (D) and the source connection (S),
C GD is the capacitance between the gate connection (G) and the drain connection (D), C GS is the capacitance between the gate connection (G) and the source connection (S), C DS is the capacitance between the drain connection (D) and the source connection (S),
wherein the values C, R MIM , R ON , R G , R GS , R GD , R D , r DS , C GD , C GS , C DS are optimized according to the equation
Q
ON
=
1
ω
·
(
1
a
R
MIM
+
n
·
1
a
R
ON
·
1
a
·
R
a
n
·
1
a
R
ON
+
1
a
R
a
)
·
a
·
C
when the semiconductor switches (SW) are open and according to the equation
Q
OFF
=
1
ω
·
(
1
a
R
MIM
+
n
1
a
R
d
+
n
ω
2
a
2
C
d
2
1
a
R
e
+
n
3
ω
2
a
2
C
d
2
1
a
R
a
)
·
a
C
d
·
a
·
C
a
C
d
+
n
·
a
2
C
when the semiconductor switches (SW) are closed, wherein
R
a
=
R
G
·
C
GD
+
C
GS
C
GD
R
b
=
R
G
·
C
GD
+
C
GS
C
GS
R
d
=
R
c
(
1
+
C
DS
C
c
)
2
C
d
=
C
DS
+
C
c
R
e
=
r
DS
R
D
r
DS
+
R
D
R
c
=
R
GD
1
+
(
ω
R
GD
C
GD
)
2
+
R
GS
1
+
(
ω
R
GS
C
GS
)
2
-
1
ω
2
R
G
C
GD
C
GS
C
c
=
C
GD
C
GS
C
GD
+
C
GS
and n is a natural number ≧1, m is an integer ≧0 and <n and a is a real number >1.