Controlling diamond film surfaces and layering
View Patent ↗A method comprising: providing at least one first diamond film comprising polycrystalline diamond, e.g., nanocrystalline or ultrananocrystalline diamond, disposed on a substrate, wherein the first diamond film comprises a surface comprising diamond asperities and having a first diamond film thickness, removing asperities from the first diamond film to form a second diamond film having a second diamond film thickness, wherein the second thickness is either substantially the same as the first thickness, or the second thickness is about 100 nm or less thinner than the first diamond film thickness, optionally patterning the second diamond film to expose substrate regions and, optionally, depositing semiconductor material on the exposed substrate regions, and depositing a solid layer on the second diamond film to form a first layered structure. Applications include for example dielectric isolation in the semiconductor industry, as well as surface acoustic wave devices, scanning probe microscope, and atomic force microscope devices.
1. A device comprising:
an insulating substrate;
at least one semiconductor layer;
one or more SiO 2 bonding layers; and
a dielectric UNCD layer disposed between the semiconductor layer and the substrate, the dielectric UNCD layer being in direct contact with at least one of the one or more SiO 2 bonding layers at an interface,
wherein a surface of the dielectric UNCD layer at the interface has a surface roughness of less than 50 nm.
2. The device according to claim 1 , wherein the one or more SiO 2 bonding layers comprise at least two SiO 2 bonding layers bonded to each other, each of the at least two SiO 2 bonding layers having a thickness of between about 50 nm and about 500 nm.
3. The device according to claim 1 , wherein the dielectric UNCD layer is in direct contact with the insulating substrate.
4. The device according to claim 1 , wherein the dielectric UNCD layer is in direct contact with the at least one semiconductor layer.
5. The device of claim 1 , wherein:
the one or more SiO 2 bonding layers comprise at least two SiO 2 bonding layers, a first SiO 2 bonding layer and a second SiO 2 bonding layer, bonded to each other, each of the at least two SiO 2 bonding layers having a thickness of between about 50 nm and about 500 nm,
the first SiO 2 bonding layer is in direct contact with the dielectric UNCD layer, and
the second SiO 2 bonding layer is in direct contact with the at least one semiconductor layer.
6. The device of claim 1 , wherein:
the one or more SiO 2 bonding layers comprise at least two SiO 2 bonding layers, a first SiO 2 bonding layer and a second SiO 2 bonding layer, bonded to each other, each of the at least two SiO 2 bonding layers having a thickness of between about 50 nm and about 500 nm,
the device comprises an additional dielectric UNCD layer, such that the device includes a first dielectric UNCD layer and a second dielectric UNCD layer,
the first SiO 2 bonding layer is in direct contact with the first dielectric UNCD layer,
the second SiO 2 bonding layer is in direct contact with the second dielectric UNCD layer, and
the second dielectric UNCD layer is in direct contact with the at least one semiconductor layer.
7. The device of claim 1 , wherein the dielectric UNCD layer is substantially free of asperities.
8. The device of claim 1 , wherein the substrate comprises sapphire and a silicon interlayer disposed thereon.
9. The device of claim 1 , wherein the at least one semiconductor layer comprises a plurality of semiconducting device elements disposed in a silicon layer.
10. The device of claim 1 , wherein the at least one semiconductor layer comprises a plurality of semiconducting device elements disposed in a silicon layer which has been etched and the etched regions filled with NCD or UNCD.
11. The device according to claim 1 , wherein the device is an integrated circuit device.
12. The device according to claim 1 , wherein the device is a surface acoustic wave device.
13. The device according to claim 1 , wherein the device is an atomic force microscope device.
14. The device according to claim 1 , wherein the device is a scanning probe microscope device.
15. The device of claim 1 , wherein the dielectric UNCD layer has a thickness of about 200 nm to about 4 microns.
16. The device of claim 1 , wherein the dielectric UNCD layer is thicker than the thickness of at least one of the one or more SiO 2 bonding layers.
17. The device of claim 1 , wherein a temperature differential between a heat producing area of the device and a surface of the dielectric UNCD layer that is opposite the heat producing area is 7.8° C. or less.
18. The device of claim 1 , wherein a temperature differential between a heat producing area of the device and a surface of the dielectric UNCD layer that is opposite the heat producing area is 3.9° C. or less.
19. The device of claim 1 , wherein the surface of the dielectric UNCD layer at the interface has a surface roughness of less than 10 nm.
20. A device comprising:
an insulating substrate;
at least one semiconductor layer;
one or more Cu bonding layers; and
a dielectric UNCD layer disposed between the semiconductor layer and the substrate, the dielectric UNCD layer being in direct contact with at least one of the one or more Cu bonding layers at an interface,
wherein a surface of the dielectric UNCD layer at the interface has a surface roughness of less than 50 nm.
21. The device of claim 17 , wherein a temperature differential between a heat producing area of the device and a surface of the dielectric UNDC layer that is opposite the heat producing area is 0.1° C. or less.
22. The device of claim 17 , wherein a temperature differential between a heat producing area of the device and a surface of the dielectric UNDC layer that is opposite the heat producing area is lower than a temperature differential of a bulk silicon device.
23. A device comprising:
an insulating substrate;
at least one semiconductor layer;
one or more SiO 2 bonding layers; and
a dielectric UNCD layer disposed between the semiconductor layer and the substrate, the dielectric UNCD layer being in direct contact with at least one of the one or more SiO 2 bonding layers at an interface,
wherein an average grain size of the UNCD of the dielectric UNCD layer is less than 50 nm.