Thin film transistor substrate and method of manufacturing thereof

1. A method of manufacturing a thin film transistor substrate, the method comprising:

forming a gate line and a data line intersecting each other with a gate insulating layer interposed and defining a pixel area on the substrate, a thin film transistor electrically connected to the gate line and the data line, and a stepped-structure occurring pattern overlapping with at least one of the gate line and the data line;

forming a passivation layer having a stepped-structure portion formed by the stepped-structure occurring pattern on the substrate;

forming a photoresist pattern having a second stepped-structure portion corresponding to the stepped-structure portion on the passivation layer;

patterning the passivation layer using the photoresist pattern as a mask;

forming a transparent conductive layer on the substrate; and

removing the photoresist pattern where the transparent conductive layer is covered by a stripper penetrating through the stepped-structure portion of the photoresist pattern and forming a pixel electrode connected to the thin film transistor.

2. The method of claim 1 , wherein the forming of the gate line, the data line, the thin film transistor, and the stepped-structure occurring pattern comprises:

forming a gate metal pattern including the gate line, the gate electrode of the thin film transistor, and the stepped-structure occurring pattern on the substrate; and

forming a gate insulating layer covering the gate line, the gate electrode, and the stepped-structure occurring pattern, forming the semiconductor pattern on the gate insulating layer, and forming source/drain metal patterns including the data line overlapping with the stepped-structure occurring pattern, a source electrode and a drain electrode of the thin film transistor on the semiconductor pattern.

3. The method of claim 1 , wherein the forming of the gate line, the data line, the thin film transistor, and the stepped-structure occurring pattern comprises:

forming a gate metal pattern including the gate line and the gate electrode of the thin film transistor on the substrate; and

forming a gate insulating layer covering the gate line and the gate electrode, forming the semiconductor pattern on the gate insulating layer, and forming source/drain metal patterns including the stepped-structure occurring pattern overlapping with the gate line, the data line, a source electrode and a drain electrode of the thin film transistor on the semiconductor pattern.

4. The method of claim 2 or 3 , wherein the semiconductor pattern is patterned with the source/drain metal patterns by one mask process using a slit mask or a half-tone mask.

5. The method of claim 1 , wherein the stepped-structure occurring patterns are spaced apart from each other.

6. The method of claim 5 , further comprising a connecting pattern formed between the stepped-structure occurring patterns so as to connect the stepped-structure occurring patterns to each other.

7. The method of claim 6 , wherein the width of the connecting pattern is constant or gradually increases toward the stepped-structure occurring patterns.